Title:

Semiconductor memory including ferroelectric gate capacitor structure, and method of fabricating the same

Document Type and Number:

United States Patent Application 20020038402

Kind Code:

Abstract:

A semiconductor memory including a ferroelectric gate capacitor structure includes an insulating interlayer formed on the surface of a semiconductor substrate. The insulating interlayer includes a hole at a position corresponding to a channel region. In the channel length direction, the hole extends across the channel region. A ferroelectric gate capacitor structure is formed in the hole. The ferroelectric gate capacitor structure includes a dielectric film, ferroelectric film, and upper electrode formed in this order from the substrate side.

Inventors:

Kanaya, Hiroyuki (Yokohama-shi, JP)

Plaque It!

What is claimed is:

1. A semiconductor memory including a ferroelectric gate capacitor structure, comprising: a semiconductor substrate; a source layer and a drain layer formed in a surface of said substrate, said source layer and said drain layer opposing each other in a channel length direction with a channel region in the surface of said substrate interposed therebetween; an insulating interlayer formed on said surface of said substrate to extend from said source layer to said drain layer, said insulating interlayer including a hole at a position corresponding to said channel region, and said hole extending across said channel region in said channel length direction; a capacitor insulating film comprising a ferroelectric film and formed to cover bottom and side surfaces of said hole, said capacitor insulating film including a first recess at a position corresponding to said channel region; an upper electrode formed to cover bottom and side surfaces of said first recess; and a dielectric film formed between said substrate and said capacitor insulating film to cover said bottom surface of said hole.

2. The memory according to claim 1, wherein said bottom surface of said hole is defined by said surface of said substrate.

3. The memory according to claim 1, wherein said dielectric film is formed to cover said bottom and side surfaces of said hole.

4. The memory according to claim 1, further comprising a lower electrode formed between said dielectric film and said capacitor insulating film to cover said bottom surface of said hole.

5. The memory according to claim 4, wherein said lower electrode is formed to cover said bottom and side surfaces of said hole.

6. The memory according to claim 1, further comprising a conductive contact plug formed on said upper electrode, wherein said upper electrode includes a second recess for receiving said contact plug.

7. The memory according to claim 6, wherein said contact plug is in contact with bottom and side surfaces of said second recess in said upper electrode.

8. The memory according to claim 1, further comprising a wiring layer formed above said capacitor insulating film and said upper electrode, and a hydrogen barrier layer interposed between said capacitor insulating film and said wiring layer, and between said upper electrode and said wiring layer.

9. The memory according to claim 8, wherein said hydrogen barrier layer comprises a material selected from the group consisting of Al_xO_y, Al_xSi_yO_z, TiO_x, ZrO_x, MgO_x, and MgTiO_x.

10. The memory according to claim 8, further comprising another insulating interlayer formed between said capacitor insulating film and said hydrogen barrier layer, and between said upper electrode and said hydrogen barrier layer.

11. A semiconductor memory including a ferroelectric gate capacitor structure, comprising: a semiconductor substrate; a source layer and a drain layer formed in a surface of said substrate, said source layer and said drain layer opposing each other in a channel length direction with a channel region in the surface of said substrate interposed therebetween; an insulating interlayer formed on said surface of said substrate to extend from said source layer to said drain layer, said insulating interlayer including a hole at a position corresponding to said channel region, and said hole extending across said channel region in said channel length direction; a capacitor insulating film comprising a ferroelectric film formed to cover a bottom surface of said hole and contact side surfaces of said hole; and an upper electrode formed to cover said capacitor insulating film in said hole and contact said side surfaces of said hole, wherein said capacitor insulating film and said upper electrode have different lengths in said channel length direction, and first and second portions of said hole on the same level as said capacitor insulating film and said upper electrode have different lengths in said channel length direction.

12. The memory according to claim 11, wherein said bottom surface of said hole is defined by said surface of said substrate.

13. The memory according to claim 11, further comprising a dielectric film formed between said substrate and said capacitor insulating film to cover the bottom surface of said hole.

14. The memory according to claim 13, wherein said dielectric film has a length different from that of said capacitor insulating film in said channel length direction.

15. The memory according to claim 13, further comprising a lower electrode formed between said dielectric film and said capacitor insulating film to cover said bottom surface of said hole.

16. The memory according to claim 15, wherein said dielectric film includes a recess at a position corresponding to said channel region, and said lower electrode is formed to cover bottom and side surfaces of said recess.

17. The memory according to claim 11, wherein said first and second portions of said hole are formed in first and second portions, respectively, of said insulating interlayer formed in different steps.

18. The memory according to claim 11, wherein said upper electrode has a larger length than that of said capacitor insulating film in said channel length direction.

19. The memory according to claim 14, said dielectric film has a larger length than that of said capacitor insulating film in said channel length direction.

20. The memory according to claim 19, wherein said upper electrode has a larger length than that of said capacitor insulating film in said channel length direction.

21. A method of fabricating a semiconductor memory including a ferroelectric gate capacitor structure, comprising: forming a source layer and a drain layer in a surface of a semiconductor substrate, said source layer and said drain layer opposing each other in a channel length direction with a channel region in said surface of said substrate interposed therebetween; forming, on said surface of said substrate, an insulating interlayer extending from said source layer to said drain layer and including a hole at a position corresponding to said channel region, said hole extending across said channel region in said channel length direction; sequentially stacking a dielectric film, a capacitor insulating film comprising a ferroelectric film, and an upper electrode film on said insulating interlayer to cover bottom and side surfaces of said hole; and removing portions of said dielectric film, said capacitor insulating film, and said upper electrode film on said insulating interlayer by planarization.

22. The method according to claim 21, further comprising forming a lower electrode film between said dielectric film and said ferroelectric film by deposition, to cover said bottom and side surfaces of said hole.

23. The method according to claim 21, wherein said bottom surface of said hole is defined by said surface of said substrate.

24. The method according to claim 21, wherein said hole in said insulating interlayer is formed by forming a sacrificial structure at a position on said substrate corresponding to said channel region, forming said insulating interlayer on said substrate to surround said sacrificial structure, and removing said sacrificial structure by etching.

25. The method according to claim 24, wherein said source layer and said drain layer are formed by implanting impurity ions into said surface of said substrate by using said sacrificial structure as a mask.

26. A method of fabricating a semiconductor memory including a ferroelectric gate capacitor structure, comprising: forming a source layer and a drain layer in a surface of a semiconductor substrate, said source layer and said drain layer opposing each other in a channel length direction with a channel region in said surface of said substrate interposed therebetween; forming, on or above the surface of said substrate, a first insulating interlayer extending from said source layer to said drain layer and including a first recess at a position corresponding to said channel region; stacking a capacitor insulating film comprising a ferroelectric film on said first insulating interlayer to cover bottom and side surfaces of said first recess; removing a portion of said capacitor insulating film on said first insulating interlayer by planarization, thereby leaving said capacitor insulating film in said first recess; forming, on said first insulating interlayer and said capacitor insulating film, a second insulating interlayer including a second recess at a position corresponding to said channel region and exposing said capacitor insulating film, said first and second recesses having different lengths in said channel length direction; depositing an upper electrode film on said second insulating interlayer to cover bottom and side surfaces of said second recess; and removing a portion of said upper electrode film on said second insulating interlayer by planarization.

27. The method according to claim 26, further comprising, before said first insulating interlayer is formed: forming, on the surface of said substrate, a third insulating interlayer extending from said source layer to said drain layer and including a third recess at a position corresponding to said channel region; depositing a dielectric film on said third insulating interlayer to cover bottom and side surfaces of said third recess; and removing a portion of said dielectric film on said third insulating interlayer by planarization, thereby leaving said dielectric film in said third recess, wherein said first insulating interlayer is formed on said third insulating interlayer.

28. The method according to claim 27, wherein said third recess has a length different from that of said first recess in said channel length direction.

29. The method according to claim 26, further comprising, before said first insulating interlayer is formed: forming, on the surface of said substrate, a third insulating interlayer extending from said source layer to said drain layer and including a third recess at a position corresponding to said channel region; forming a dielectric film and a lower electrode film in this order on said third insulating interlayer by deposition, to cover said bottom and side surfaces of said third recess; and removing portions of said dielectric film and said lower electrode film on said third insulating interlayer by planarization, wherein said first insulating interlayer is formed on said third insulating interlayer.

30. The method according to claim 29, wherein said third recess has a length different from that of said first recess in said channel length direction.

31. The method according to claim 26, wherein said first recess in said first insulating interlayer is formed by forming a sacrificial structure at a position on said substrate corresponding to said channel region, forming said first insulating interlayer on said substrate to surround said sacrificial structure, and removing said sacrificial structure by etching.

32. The method according to claim 31, wherein said source layer and said drain layer are formed by implanting impurity ions into said surface of said substrate by using said sacrificial structure as a mask.

Description:

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor memory including a ferroelectric gate capacitor structure in which a ferroelectric capacitor is incorporated into the gate structure of a transistor, and a method of fabricating the same.

[0003] 2. Description of the Related Art

[0004] In a semiconductor memory including a ferroelectric gate capacitor structure, a ferroelectric capacitor is formed on a transistor. Since a unit cell has only the area of one transistor, therefore, the structure effectively increases the degree of integration. However, the techniques of fabricating semiconductor memories including a ferroelectric gate capacitor structure still have many problems, so such memories have not been fabricated into products yet.

[0005] In the formation of this ferroelectric gate capacitor structure, methods using etching techniques are often used. One example of processes of fabricating semiconductor memories including a conventional ferroelectric gate capacitor structure will be described below with reference to sectional views in FIGS. 40A and 40B .

[0006] As shown in FIG. 40 A, on the entire surface of a silicon substrate 301 in which a source layer 301 a and a drain layer 301 b are formed, a 5-nm thick dielectric film 302 made of Bi ₂ SiO ₅ is formed by CVD or the like. A 10-nm thick Pt film (electrode film) 303 is then formed on the entire surface by using CVD or the like. A 30-nm thick ferroelectric film 304 made of SrBi ₂ Ta ₂ O ₉ is formed on the entire surface by using CVD or the like. A 10-nm thick Pt film (electrode film) 305 is formed on the entire surface by using CVD or the like.

[0007] Subsequently, these dielectric film 302 , Pt film 303 , ferroelectric film 304 , and Pt film 305 are selectively removed by dry etching such as RIE (Reactive Ion Etching) by using an oxide film or a resist 306 as a mask. Consequently, the source layer 301 a and the drain layer 301 b are partially exposed.

[0008] As shown in FIG. 40 B, an insulating interlayer 307 is deposited on the entire surface of the device. This insulating interlayer 307 is selectively removed to form trenches 308 d to 308 f having a predetermined depth. The insulating interlayer 307 is again selectively removed to form a contact hole 308 a reaching the source layer 301 a, a contact hole 308 b reaching the drain layer 301 b, and a contact hole 308 c reaching the Pt film 305 . A metal is deposited in a range including the interiors of the contact holes 308 a to 308 c and the trenches 308 d to 308 f. After that, the surface of the device is planarized to expose the insulating interlayer 307 . Consequently, contact plugs 311 a to 311 c and lines 311 d to 311 f are formed.

[0009] If, however, RIE is used as dry etching in the step shown in FIG. 40 A, plasma damage or chemical damage happens to the dielectric film 302 , the Pt film 303 , the ferroelectric film 304 , and the Pt film 305 . If this dry etching is excessively done, damage also happens to the source layer 301 a and the drain layer 301 b.

[0010] As described above, the conventional ferroelectric gate capacitor structure formation process readily causes damage. This damage becomes conspicuous as microfabrication advances, leading to a lowering of the reliability.

[0011] A ferroelectric capacitor is representatively formed using platinum (Pt) as upper and lower electrodes and a PZT (PbZr _1-x TiO _x ) film as a ferroelectric film. To form an FeRAM by an LSI process using a silicon substrate, the surface of the silicon substrate is covered with an insulating film such as an oxide film. On this insulating film, a lower Pt electrode, PZT film, and upper Pt electrode are formed by patterning, thereby fabricating a ferroelectric capacitor. Usually, a Ti or TiO _X film is formed below the lower Pt electrode to improve the adhesion.

[0012] In this conventional ferroelectric capacitor, a reducing gas such as hydrogen contained in the Si-LSI process deteriorates the ferroelectric characteristic. More specifically, the spontaneous polarization amount reduces. To prevent this deterioration of the characteristic of a ferroelectric capacitor caused by hydrogen reduction, several countermeasures which prevent invasion of hydrogen and the like into the capacitor have been conventionally proposed. However, none of them is simple and reliable.

[0013] In addition to this characteristic deterioration by hydrogen reduction, the characteristics of a ferroelectric capacitor deteriorate by process damage as described earlier. For example, Jpn. Pat. Appln. KOKAI Publication No. 8-335673 discloses a method which, in order to prevent interdiffusion between a ferro-electric capacitor such as PZT and an SiO ₂ insulating film, covers the ferroelectric capacitor with a diffusion preventing film so that the capacitor and the insulating film do not directly contact each other. This reference describes that TiO ₂ , ZrO ₂ , Al ₂ O ₃ , and the like are effective as the diffusion preventing film. However, the problem in this reference is peeling of the capacitor ferroelectric film by interdiffusion; the reference does not regard deterioration of the ferroelectric capacitor characteristic by hydrogen reduction occurring in the fabrication process as a problem.

[0014] Recent research by the present inventors has revealed that using TiO _X as an adhesive layer between a ferroelectric capacitor and an SiO ₂ insulating film brings about several inconveniences. For example, the ferroelectric characteristic deteriorates when Ti diffuses into a PZT film.

BRIEF SUMMARY OF THE INVENTION

[0015] According to the first aspect of the present invention, there is provided a semiconductor memory including a ferroelectric gate capacitor structure, comprising

[0016] a semiconductor substrate,

[0017] a source layer and a drain layer formed in a surface of the substrate, the source layer and the drain layer opposing each other in a channel length direction with a channel region in the surface of the substrate interposed therebetween,

[0018] an insulating interlayer formed on the surface of the substrate to extend from the source layer to the drain layer, the insulating interlayer including a hole at a position corresponding to the channel region, and the hole extending across the channel region in the channel length direction,

[0019] a capacitor insulating film comprising a ferroelectric film and formed to cover bottom and side surfaces of the hole, the capacitor insulating film including a first recess at a position corresponding to the channel region,

[0020] an upper electrode formed to cover bottom and side surfaces of the first recess, and

[0021] a dielectric film formed between the substrate and the capacitor insulating film to cover the bottom surface of the hole.

[0022] According to the second aspect of the present invention, there is provided a semiconductor memory including a ferroelectric gate capacitor structure, comprising

[0023] a semiconductor substrate,

[0024] a source layer and a drain layer formed in a surface of the substrate, the source layer and the drain layer opposing each other in a channel length direction with a channel region in the surface of the substrate interposed therebetween,

[0025] an insulating interlayer formed on the surface of the substrate to extend from the source layer to the drain layer, the insulating interlayer including a hole at a position corresponding to the channel region, and the hole extending across the channel region in the channel length direction,

[0026] a capacitor insulating film comprising a ferroelectric film formed to cover a bottom surface of the hole and contact side surfaces of the hole, and

[0027] an upper electrode formed to cover the capacitor insulating film in the hole and contact the side surfaces of the hole,

[0028] wherein the capacitor insulating film and the upper electrode have different lengths in the channel length direction, and first and second portions of the hole on the same level as the capacitor insulating film and the upper electrode have different lengths in the channel length direction.

[0029] According to the third aspect of the present invention, there is provided a method of fabricating a semiconductor memory including a ferroelectric gate capacitor structure, comprising

[0030] forming a source layer and a drain layer in a surface of a semiconductor substrate, the source layer and the drain layer opposing each other in a channel length direction with a channel region in the surface of the substrate interposed therebetween,

[0031] forming, on the surface of the substrate, an insulating interlayer extending from the source layer to the drain layer and including a hole at a position corresponding to the channel region, the hole extending across the channel region in the channel length direction,

[0032] sequentially stacking a dielectric film, a capacitor insulating film comprising a ferroelectric film, and an upper electrode film on the insulating interlayer to cover bottom and side surfaces of the hole, and

[0033] removing portions of the dielectric film, the capacitor insulating film, and the upper electrode film on the insulating interlayer by planarization.

[0034] According to the fourth aspect of the present invention, there is provided a method of fabricating a semiconductor memory including a ferroelectric gate capacitor structure, comprising

[0035] forming a source layer and a drain layer in a surface of a semiconductor substrate, the source layer and the drain layer opposing each other in a channel length direction with a channel region in the surface of the substrate interposed therebetween,

[0036] forming, on or above the surface of the substrate, a first insulating interlayer extending from the source layer to the drain layer and including a first recess at a position corresponding to the channel region,

[0037] stacking a capacitor insulating film comprising a ferroelectric film on the first insulating interlayer to cover bottom and side surfaces of the first recess,

[0038] removing a portion of the capacitor insulating film on the first insulating interlayer by planarization, thereby leaving the capacitor insulating film in the first recess,

[0039] forming, on the first insulating interlayer and the capacitor insulating film, a second insulating interlayer including a second recess at a position corresponding to the channel region and exposing the capacitor insulating film, the first and second recesses having different lengths in the channel length direction,

[0040] depositing an upper electrode film on the second insulating interlayer to cover bottom and side surfaces of the second recess, and

[0041] removing a portion of the upper electrode film on the second insulating interlayer by planarization.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0042] FIG. 1 is a longitudinal sectional view showing the whole construction of a semiconductor device according to the first embodiment of the present invention;

[0043] FIGS. 2A, 2B , and 2 C are sectional views showing the steps of a method of fabricating the semiconductor device according to the present invention;

[0044] FIGS. 3A and 3B are sectional views showing the steps following FIG. 2C of the method of fabricating the semiconductor device according to the first embodiment;

[0045] FIGS. 4A and 4B are sectional views showing the steps following FIG. 3B of the method of fabricating the semiconductor device according to the first embodiment;

[0046] FIG. 5 is a top view of the semiconductor device according to the first embodiment;

[0047] FIG. 6 is a graph showing the relationship between the gate voltage and drain current of a gate capacitor structure according to the first embodiment;

[0048] FIG. 7 is a graph showing the holding characteristic of the gate capacitor structure according to the first embodiment;

[0049] FIG. 8 is a longitudinal sectional view showing the whole construction of a semiconductor device according to the second embodiment of the present invention;

[0050] FIG. 9 is a sectional view showing a method of fabricating the semiconductor device according to the second embodiment;

[0051] FIG. 10 is a view showing the whole construction of a semiconductor device according to a modification of the second embodiment;

[0052] FIG. 11 is a longitudinal sectional view showing the whole construction of a semiconductor device according to the third embodiment of the present invention;

[0053] FIG. 12 is a sectional view showing a method of fabricating the semiconductor device according to the third embodiment;

[0054] FIG. 13 is a sectional view showing the first modification of the semiconductor device according to the third embodiment;

[0055] FIG. 14 is a sectional view showing the second modification of the semiconductor device according to the third embodiment;

[0056] FIGS. 15A, 15B , and 15 C are sectional views showing the third modification of the semiconductor device according to the third embodiment;

[0057] FIG. 16 is a longitudinal sectional view showing the whole construction of a semiconductor device according to the fourth embodiment of the present invention;

[0058] FIG. 17 is a sectional view showing a method of fabricating the semiconductor device according to the fourth embodiment;

[0059] FIG. 18 is a sectional view showing the first modification of the semiconductor device according to the fourth embodiment;

[0060] FIG. 19 is a sectional view showing the second modification of the semiconductor device according to the fourth embodiment;

[0061] FIG. 20 is a longitudinal sectional view showing the whole construction of a semiconductor device according to the fifth embodiment of the present invention;

[0062] FIGS. 21A, 21B , 21 C, and 21 D are sectional views showing the steps of a method of fabricating the semiconductor device according to the fifth embodiment;

[0063] FIGS. 22A, 22B , and 22 C are sectional views showing the steps following FIG. 21D of the method of fabricating the semiconductor device according to the fifth embodiment;

[0064] FIG. 23 is a longitudinal sectional view showing the whole construction of a semiconductor device according to the sixth embodiment of the present invention;

[0065] FIGS. 24A, 24B , and 24 C are sectional views showing the steps of a method of fabricating the semiconductor device according to the sixth embodiment;

[0066] FIGS. 25A and 25B are sectional views showing the steps following FIG. 24C of the method of fabricating the semiconductor device according to the sixth embodiment;

[0067] FIG. 26 is a longitudinal sectional view showing the whole construction of a semiconductor device according to the seventh embodiment of the present invention;

[0068] FIGS. 27A and 27B are sectional views showing the steps of a method of fabricating the semiconductor device according to the seventh embodiment;

[0069] FIG. 28 is a longitudinal sectional view showing the whole construction of a semiconductor device according to the eighth embodiment of the present invention;

[0070] FIG. 29 is an equivalent circuit diagram of the semiconductor device according to the eighth embodiment;

[0071] FIGS. 30A and 30B are sectional views showing the steps of a method of fabricating the semiconductor device according to the eighth embodiment;

[0072] FIGS. 31A and 31B are sectional views showing the steps following FIG. 30B of the method of fabricating the semiconductor device according to the eighth embodiment;

[0073] FIG. 32 is a longitudinal sectional view showing the whole construction of a semiconductor device according to the ninth embodiment of the present invention;

[0074] FIGS. 33A, 33B , and 33 C are sectional views showing the steps of a method of fabricating the semiconductor device according to the ninth embodiment;

[0075] FIGS. 34A and 34B are sectional views showing the steps following FIG. 33C of the method of fabricating the semiconductor device according to the ninth embodiment;

[0076] FIGS. 35A and 35B are sectional views showing the steps following FIG. 34B of the method of fabricating the semiconductor device according to the ninth embodiment;

[0077] FIG. 36 is a view showing, in enlarged scale, a capacitor and its vicinity of a semiconductor device according to a modification of the ninth embodiment;

[0078] FIG. 37 is a longitudinal sectional view showing the whole construction of a semiconductor device according to the 10th embodiment of the present invention;

[0079] FIG. 38 is a longitudinal sectional view showing the whole construction of a semiconductor device according to the 11th embodiment of the present invention;

[0080] FIG. 39 is a longitudinal sectional view showing the whole construction of a semiconductor device according to the 12th embodiment of the present invention; and

[0081] FIGS. 40A and 40B are sectional views for explaining problems of a conventional semiconductor device fabrication method.

DETAILED DESCRIPTION OF THE INVENTION

[0082] Embodiments of the present invention will be described below with reference to the accompanying drawings. In the following description, the same reference numerals denote parts having substantially the same functions and arrangements, and a duplicate explanation will be made only where necessary. Also, a detailed description of common fabrication steps will be omitted.

[0083] First Embodiment

[0084] FIG. 1 is a longitudinal sectional view showing the whole construction of a semiconductor device according to the first embodiment of the present invention. In this embodiment, the present invention is applied to an MFMIS (electrode/ferroelectric film/electrode/dielectric film/semiconductor) structure.

[0085] As shown in FIG. 1, a source layer 1 a and a drain layer 1 b are formed in the surface of an Si substrate 1 . These source layer 1 a and drain layer 1 b oppose each other in the channel length direction on the two sides of a channel region 1 c in the surface of the substrate 1 . An insulating interlayer 3 is formed on the Si substrate 1 . A trench (hole) is formed in this insulating interlayer 3 . On the Si substrate 1 , this trench is formed from a portion above the channel region 1 c so as to overlap portions of the source layer 1 a and the drain layer lb. In this trench, a 5-nm thick dielectric film 4 made of, e.g., Bi ₂ SiO ₅ is formed to cover the bottom and side surfaces of the trench. In addition, a 10-nm thick Pt film (lower electrode film) 5 is formed to cover the bottom and side surfaces of a recess in this dielectric film 4 . Also, a 30-nm thick SBT ferroelectric film 6 is formed to cover the bottom and side surfaces of a recess in this Pt film 5 . Furthermore, a 10-nm thick Pt film (upper electrode film) 7 is formed to cover the bottom and side surfaces of this ferroelectric film 6 . The trench is filled with these dielectric film 4 , Pt film 5 , ferroelectric film 6 , and Pt film 7 . Each of the dielectric film 4 , the Pt film 5 , and the dielectric film 6 has a U sectional shape. Note that in the following description, a component simply called a dielectric film indicates a dielectric film having no ferroelectricity, e.g., a high-dielectric film.

[0086] An insulating interlayer 8 is formed on the insulating interlayer 3 . Contact plugs 8 a to 8 c are formed in these insulating interlayers 3 and 8 . That is, the contact plug 8 a is formed by burying a metal in a contact hole reaching the source layer 1 a through the insulating interlayers 3 and 8 . The contact plug 8 b is formed by burying a metal in a contact hole reaching the drain 1 b through the insulating interlayers 3 and 8 . The contact plug 8 c is formed by burying a metal in a contact hole reaching the Pt film 7 through the insulating interlayer 8 . Also, trenches are formed in this insulating interlayer 8 so as to overlap these contact plugs 8 a to 8 c. In these trenches, lines 9 a to 9 c electrically connected to the contact plugs 8 a to 8 c are formed.

[0087] A method of fabricating the semiconductor device according to this embodiment will be described below with reference to sectional views shown in FIGS. 2A to 4 B.

[0088] First, as shown in FIG. 2A, a poly-Si layer 2 a and an SiN layer 2 b are sequentially stacked on the entire surface of an Si substrate 1 . These poly-Si layer 2 a and SiN layer 2 b are selectively left on the Si substrate 1 by patterning. A stacked structure of the selectively left SiN layer 2 b and poly-Si layer 2 a functions as a dummy gate (sacrificial structure) 2 . This stacked structure of the layers 2 a and 2 b will be called a dummy gate 2 hereinafter. Note that, although not shown, a gate oxide film 2 is formed on the surface of the Si substrate 1 throughout the following embodiments.

[0089] As shown in FIG. 2 B, this dummy gate 2 is used as a mask to form a source layer 1 a and a drain layer 1 b in the surface of the Si substrate 1 , by doping an impurity into the surface of the substrate 1 by ion implantation or the like. An insulating interlayer 3 is deposited on the Si substrate 1 in which the source layer 1 a and the drain layer 1 b are formed. The surface of this insulating interlayer 3 is planarized to expose the dummy gate 2 . In this planarization step, the SiN layer 2 b functions as a stopper.

[0090] As shown in FIG. 2 C, the dummy gate 2 is selectively removed while the insulating interlayer 3 is left behind. This step of removing the dummy gate 2 is done by using wet etching and CDE (Chemical Dry Etching). Since the removal is thus performed without using RIE, damage to the source layer 1 a and the drain layer 1 b is reduced. A ferroelectric capacitor is formed by removing the dummy gate 2 , but a portion from which this dummy gate 2 is not removed also exists. This portion from which the dummy gate 2 is not removed effectively functions as a switching transistor.

[0091] As a result of this removal of the dummy gate 2 , a trench is formed in the insulating interlayer 3 on a channel region 1 c sandwiched between the source layer 1 a and the drain layer 1 b. As shown in FIG. 3A, a dielectric film 4 , a Pt film (lower electrode film) 5 , a ferroelectric film 6 , and a Pt film (upper electrode film) 7 are sequentially stacked on the entire surface of the device. These dielectric film 4 , Pt film 5 , ferroelectric film 6 , and Pt film 7 are successively formed by CVD. Also, these dielectric film 4 , Pt film 5 , ferroelectric film 6 , and Pt film 7 are formed to be thin along the surface of the insulating interlayer 3 , and along the shape of the bottom and side surfaces of the trench so as to cover this trench with a substantially uniform film thickness. Accordingly, the dielectric film 4 , the Pt film 5 , the ferroelectric film 6 , and the Pt film 7 assume a sectional shape recessed at the depth of the trench. Furthermore, the trench has in the channel length direction (source/drain direction) a width larger than twice the sum of the film thicknesses of the dielectric film 4 , the Pt film 5 , the ferroelectric film 6 , and the Pt film 7 . That is, in this trench the upper surface of the Pt film 7 is lower than that of the insulating interlayer 3 .

[0092] Next, as shown in FIG. 3 B, the upper surface of the device is planarized by using CMP. By this planarization, the Pt film 7 , the ferroelectric film 6 , the Pt film 5 , and the dielectric film 4 on the insulating interlayer 3 are removed in this order to expose the surface of the insulating interlayer 3 . CMP is continued even after the surface of the insulating interlayer 3 is thus exposed. CMP is terminated when the upper surface of the Pt film 7 formed at the lowest position in the trench is planarized and leveled with the surrounding insulating interlayer 3 . The result is a structure in which the bottom and side surfaces of the trench inside the insulating interlayer 3 are covered with the dielectric film 4 , the Pt film 5 , and the ferroelectric film 6 , and the Pt film 7 is buried in the recess of the ferroelectric film 6 (the bottom and side surfaces of the recess are covered with the Pt film 7 ). These dielectric film 4 , Pt film 5 , ferroelectric film 6 , and Pt film 7 implement a gate capacitor structure 10 . The characteristics of the capacitor are further improved if oxygen recovery annealing (600° C.) is performed after that.

[0093] As shown in FIG. 4 A, an insulating interlayer 8 is deposited on the insulating interlayer 3 and the gate capacitor structure 10 . Next, as shown in FIG. 4 B, trenches having the surface of this insulating interlayer 8 as their bottom surfaces are formed. Contact holes reaching the source layer 1 a and the drain layer 1 b through the insulating interlayers 3 and 8 are formed. Similarly, a contact hole reaching the gate capacitor structure 10 through the insulating interlayer 8 is formed. A metal is buried in these contact holes and trenches to form contact plugs 8 a to 8 c and lines 9 a to 9 c. In this manner, the semiconductor device shown in FIG. 1 is implemented.

[0094] FIG. 5 shows the top view of the semiconductor device thus implemented. FIG. 5 is obtained by cutting the device between the insulating interlayers 3 and 8 except for the contact plug 8 c formed on the insulating interlayer 3 and electrically connected to the gate capacitor structure 10 . This contact plug 8 c is shown in FIG. 5 in order to clarify the positional relationship to other components. As shown in FIG. 5 , in an active region 51 , the gate capacitor structure 10 is formed between the contact plugs 8 a and 8 b. Also, in this gate capacitor structure 10 , the Pt film 7 is formed inside the ferroelectric film 6 , the ferroelectric film 6 is formed inside the Pt film 5 , and the Pt film 5 is formed inside the dielectric film 4 . However, this embodiment is of course not restricted to the arrangement shown in FIG. 5 .

[0095] FIG. 6 shows the characteristic of the semiconductor device including the ferroelectric gate capacitor structure fabricated through the above steps. FIG. 6 is a graph showing the memory window of this gate structure, in which the gate voltage is plotted on the abscissa and the drain current on the ordinate. As shown in FIG. 6 , the memory window of the gate structure of this embodiment is 4 V, indicating an excellent characteristic.

[0096] FIG. 7 shows the holding characteristic of the gate structure of this embodiment. The abscissa indicates time, and the ordinate indicates the drain current. The broken lines show the characteristic of a conventional structure, and the solid lines show the characteristic of the gate structure according to this embodiment. As shown in FIG. 7 , in the conventional structure no drain current sufficient for data read can be obtained when the semiconductor device is left to stand for only a few years, much shorter than 10 years. In contrast, the structure of this embodiment has a holding characteristic of 10 years or more. That is, the structure of this embodiment has a holding characteristic far better than that of the conventional structure.

[0097] In this embodiment as described above, the insulating interlayer 3 is selectively formed using the dummy gate 2 , and the gate capacitor structure 10 is formed in a trench from which the dummy gate 2 is removed. This obviates the need for an etching process in the formation of the gate capacitor structure 10 , so neither plasma damage nor chemical damage caused by the use of RIE or the like takes place. Also, when this gate capacitor structure 10 is formed, the insulating interlayer 3 covers most of the source layer 1 a and the drain layer 1 b. Accordingly, damage occurring when the gate capacitor structure 10 is formed has almost no influence on the source layer 1 a and the drain layer 1 b.

[0098] Second Embodiment

[0099] This embodiment relates to a modification of the first embodiment and is characterized in a gate capacitor structure. The rest of the structure and the fabrication process are the same as the first embodiment. Like the first embodiment, a semiconductor device of this embodiment is an example of an MFMIS structure.

[0100] FIG. 8 is a sectional view showing the whole construction of the semiconductor device of this embodiment. As shown in FIG. 8 , components forming a gate capacitor structure 81 of this embodiment are a dielectric film 4 , a Pt film 5 , a ferroelectric film 6 , and a Pt film 7 . This is the same as the first embodiment. This embodiment differs from the first embodiment in that the surface of the Pt film 7 is not flat, but the section of this Pt film 7 has a recessed shape defined by its bottom and side surfaces. That is, in this embodiment, all of the dielectric film 4 , the Pt film 5 , the ferroelectric film 6 , and the Pt film 7 have a sectional shape recessed near the center of the trench. A contact plug 8 c enters the recess of the Pt film 7 and contacts its bottom surface.

[0101] The fabrication steps of the semiconductor device according to this embodiment are the same as the first embodiment from the step shown in FIG. 2A to the step shown in 3 A. A difference of this embodiment resides in the step of planarizing the entire surface of the device after the step shown in FIG. 3A . In this embodiment, after the step shown in FIG. 3A the whole device surface is planarized by CMP as shown in FIG. 9 . In this planarization, the Pt film 7 , the ferroelectric film 6 , the Pt film 5 , and the dielectric film 4 on an insulating interlayer 3 are sequentially removed until the insulating interlayer 3 is exposed. After the insulating interlayer 3 is exposed, the planarization step is terminated before the plane of planarization reaches the surface of the Pt film 7 . In other words, the CMP step is stopped after the surface of the insulating interlayer 3 is exposed and before the surface of the Pt film 7 is removed by CMP. Consequently, as shown in FIG. 9 , the Pt film 7 having a U sectional shape formed along the line of the bottom and side surfaces of the ferroelectric film 6 is obtained. Note that the plane of planarization means a plane on which planarization by CMP actually progresses.

[0102] After the gate capacitor structure 81 shown in FIG. 9 is obtained, an insulating interlayer 8 is deposited. The steps performed after that are the same as in the first embodiment.

[0103] In this embodiment as described above, CMP is terminated before the plane of planarization by CMP reaches the upper surface of the recess in the Pt film 7 . This can prevent a decrease of the film thickness of this Pt film 7 (upper electrode) by CMP.

[0104] The semiconductor device of this embodiment is not limited to the structure shown in FIG. 8 . FIG. 10 is a sectional view showing a modification of this embodiment. A semiconductor device shown in FIG. 10 differs from the semiconductor device shown in FIG. 8 in the structure of a gate contact. As shown in FIG. 10, a contact plug 110 c of this modification has a larger contact width in the channel length direction than that of the contact plug 8 c shown in FIG. 8 . Therefore, the contact plug 110 c contacts the bottom and side surfaces of the recess in the Pt film 7 and is also formed on the surface of the ferroelectric film 6 . In addition, since the contact width of this contact plug 110 c is large, a line 9 c electrically connected to this contact plug 110 c is formed to have a line width larger than the line width shown in FIG. 8 .

[0105] As described above, even a contact plug having a large contact width, which reaches not only the Pt film 7 as an upper electrode but also the ferroelectric film 6 , can achieve the same effect as in this embodiment.

[0106] Third Embodiment

[0107] This invention relates to a modification of the first embodiment. This embodiment differs from the first embodiment in that the present invention is applied to an MFIS (electrode/ferroelectric film/dielectric film/semiconductor) structure.

[0108] FIG. 11 is a longitudinal sectional view showing the whole construction of a semiconductor device according to this embodiment. A difference of the arrangement of this semiconductor device shown in FIG. 11 from that shown in FIG. 1 resides in a gate capacitor structure. In FIG. 1, a gate capacitor structure is formed by a four-layered structure including the dielectric film 4 , the Pt film 5 , the ferroelectric film 6 , and the Pt film 7 . In FIG. 11, a gate capacitor structure is formed by a three-layered structure including a dielectric film 4 , a ferroelectric film 6 , and a Pt film 7 . The rest of the arrangement is the same as in FIG. 1 .

[0109] A method of fabricating the semiconductor device shown in FIG. 11 will be explained with reference to FIG. 12 . In this method of fabricating the semiconductor device of this embodiment, the steps shown in FIGS. 2A to 2 C of the first embodiment are similarly performed. A step shown in FIG. 12 follows the step shown in FIG. 2C .

[0110] In this step shown in FIG. 12 , like the step shown in FIG. 3 A, on the entire surface of the device including a trench formed in an insulating interlayer 3 , a dielectric film 4 , a ferroelectric film 6 , and a Pt film 7 are continuously formed to be thin along the surface of the insulating interlayer 3 , and along the shape of the bottom and side surfaces of the trench so as to cover this trench with a substantially uniform film thickness. A difference from FIG. 3A resides in that no Pt film 5 is formed between the dielectric film 4 and the ferroelectric film 6 . Accordingly, the dielectric film 4 , the ferroelectric film 6 , and the Pt film 7 have a sectional shape recessed at the depth of the trench.

[0111] Subsequently, as in the step shown in FIG. 3 B, the upper surface of the device is planarized by using CMP. This planarization is continued until the plane of planarization reaches the surface of the Pt film 7 . The result is a structure in which the bottom and side surfaces of the trench are covered with the dielectric film 4 and the ferroelectric film 6 , and the Pt film 7 is buried in the recess of the ferroelectric film 6 (the bottom and side surfaces of the recess are covered with the Pt film 7 ). These dielectric film 4 , ferroelectric film 6 , and Pt film 7 implement a gate capacitor structure. After that, an insulating interlayer 8 is deposited and contact plugs 8 a to 8 c and lines 9 a to 9 c are formed as in the first embodiment.

[0112] In this embodiment as described above, even a semiconductor device including a ferroelectric gate capacitor with an MFIS (electrode/ferroelectric film/dielectric film/semiconductor) structure can achieve the same effects as the first embodiment.

[0113] This embodiment is not limited to the arrangement shown in FIG. 11 .

[0114] FIG. 13 shows the first modification of this embodiment. The relationship between FIGS. 13 and 11 is the same as that between FIGS. 8 and 1 . That is, the structure shown in FIG. 8 is obtained by putting forward the end point of planarization of the dielectric film 4 and so forth in the CMP process shown in FIG. 1 . Likewise, the structure shown in FIG. 13 is obtained by advancing the end point of planarization of the dielectric film 4 and so forth in the CMP process shown in FIG. 11 .

[0115] FIG. 14 shows the second modification of this embodiment. The structure shown in FIG. 14 is obtained by further advancing, more than that in FIG. 13 , the end point of planarization of the dielectric film 4 and so forth in the CMP process for obtaining the construction shown in FIG. 13 . More specifically, planarization is terminated when the ferroelectric film 6 is exposed. Consequently, the fabrication of the gate capacitor structure is completed when the dielectric film 4 and the ferroelectric film 6 are left behind on the insulating interlayer 3 . The result is a gate capacitor structure in which the dielectric film 4 and the ferroelectric film 6 are stacked on the insulating interlayer 3 , and the dielectric film 4 , the ferroelectric film 6 , and the Pt film 7 having a recessed shape are buried in the trench. To obtain this second modification, the CMP removal selectivity of the Pt film 7 to the ferroelectric film 6 is desirably higher than in the first modification or in the construction shown in FIG. 11 . The “CMP removal selectivity” is the ratio of rates at which different substances are removed by CMP. In this second modification, the CMP removal selectivity of the Pt film 7 to the ferroelectric film 6 is preferably higher than in the first modification and the like, i.e., a high CMP removal rate is preferred.

[0116] The third modification of this embodiment is a structure having a gate contact with a larger contact width than shown in FIGS. 11, 13 , and 14 . FIGS. 15A to 15 C show the whole construction of the third modification. FIGS. 15A, 15B , and 15 C correspond to FIGS. 11, 13 , and 14 , respectively. Each of FIGS. 15A to 15 C has a contact plug 151 c with a contact width larger than that of the contact plug 8 c shown in FIGS. 11, 13 , and 14 . Referring to FIGS. 15B and 15C , this contact plug 151 c contacts the bottom and side surfaces of the recess in the Pt film 7 . Also, to overlap this contact plug 151 c having a large contact width, a line 152 c has a line width larger than that of the line 9 c shown in FIGS. 11, 13 , and 14 .

[0117] Fourth Embodiment

[0118] This invention relates to a modification of the first embodiment. This embodiment differs from the first embodiment in that the present invention is applied to an MFS (electrode/ferroelectric film/semiconductor) structure.

[0119] FIG. 16 is a longitudinal sectional view showing the whole construction of a semiconductor device according to this embodiment. A difference of the arrangement of this semiconductor device shown in FIG. 16 from that shown in FIG. 1 resides in a gate capacitor structure. In FIG. 1, a gate capacitor structure is formed by a four-layered structure including the dielectric film 4 , the Pt film 5 , the ferroelectric film 6 , and the Pt film 7 . In FIG. 16, a gate capacitor structure is formed by a two-layered structure including a ferroelectric film 6 and a Pt film 7 . The rest of the arrangement is the same as in FIG. 1 .

[0120] A method of fabricating the semiconductor device shown in FIG. 16 will be explained with reference to FIG. 17 . In this method of fabricating the semiconductor device of this embodiment shown in FIG. 17 , the steps shown in FIGS. 2A to 2 C are similarly performed. A step shown in FIG. 17 follows the step shown in FIG. 2C . In this step shown in FIG. 17 , like the step shown in FIG. 3 A, on the entire surface of the device including a trench formed in an insulating interlayer 3 , a ferroelectric film 6 and a Pt film 7 are continuously formed to be thin along the surface of the insulating interlayer 3 , and along the shape of the bottom and side surfaces of the trench so as to cover this trench with a substantially uniform film thickness. A difference from FIG. 3A resides in that neither a dielectric film 4 nor a Pt film 5 is formed. Accordingly, the ferroelectric film 6 and the Pt film 7 have a sectional shape recessed at the depth of the trench.

[0121] Subsequently, as in the step shown in FIG. 3 B, the upper surface of the device is planarized by using CMP. This planarization is continued until the plane of planarization reaches the surface of the Pt film 7 . The result is a structure in which the bottom and side surfaces of the trench are covered with the ferroelectric film 6 , and the Pt film 7 is buried in the recess of the ferroelectric film 6 (the bottom and side surfaces of the recess are covered with the Pt film 7 ). After that, an insulating interlayer 8 is deposited and contact plugs 8 a to 8 c and lines 9 a to 9 c are formed as in the first embodiment.

[0122] In this embodiment as described above, even a semiconductor device including a ferroelectric gate capacitor with an MFS (electrode/ferroelectric film/semiconductor) structure can achieve the same effects as the first embodiment.

[0123] This embodiment is not limited to the arrangement shown in FIG. 16 .

[0124] FIG. 18 shows the first modification of this embodiment. The relationship between FIGS. 18 and 11 is the same as that between FIGS. 8 and 1 . That is, the structure shown in FIG. 8 is obtained by putting forward the end point of planarization of the dielectric film 4 and so forth in the CMP process shown in FIG. 1 . Likewise, the structure shown in FIG. 18 is obtained by advancing the end point of planarization of the dielectric film 4 and so forth in the CMP process shown in FIG. 16 .

[0125] FIG. 19 shows the second modification of this embodiment. The structure shown in FIG. 19 is obtained by further advancing, more than that in FIG. 18 , the end point of planarization of the dielectric film 4 and so forth in the CMP process for obtaining the construction shown in FIG. 18 . More specifically, planarization is terminated when the ferroelectric film 6 is exposed. Consequently, the fabrication of the gate capacitor structure is completed when the ferroelectric film 6 is left behind on the insulating interlayer 3 . The result is a gate capacitor structure in which the ferroelectric film 6 is formed on the insulating interlayer 3 , and the ferroelectric film 6 and the Pt film 7 having a recessed shape are buried in the trench. To obtain this second modification, the CMP removal selectivity of the Pt film 7 to the ferroelectric film 6 is desirably higher than in the first modification or in the construction shown in FIG. 16 .

[0126] The third modification of this embodiment is a structure having a gate contact with a larger contact width than shown in FIGS. 16, 18 , and 19 . This structure having a wide gate contact is analogous to that shown in FIGS. 15A, 15B , and 15 C, explained in the third embodiment, which correspond to FIGS. 11, 13 , and 14 , respectively.

[0127] Fifth Embodiment FIG. 20 is a longitudinal sectional view showing the whole construction of a semiconductor device according to the fifth embodiment of the present invention. In this embodiment, the present invention is applied to an MFMIS (electrode/ferroelectric film/electrode/dielectric film/semiconductor) structure. This embodiment relates to a modification of the first embodiment. A difference from the first embodiment resides in a gate capacitor structure.

[0128] As shown in FIG. 20, a source layer 1 a and a drain layer 1 b are formed in the surface of an Si substrate 1 . These source layer 1 a and drain layer 1 b oppose each other in the channel length direction on the two sides of a channel region 1 c in the surface of the substrate 1 . An insulating interlayer 61 is formed on the Si substrate 1 . A first trench is formed in this insulating interlayer 61 . This first trench is formed on the channel region 1 c of the Si substrate 1 , where the source layer 1 a and the drain layer 1 b are not formed. In this first trench, a 5-nm thick dielectric film 4 made of, e.g., Bi ₂ SiO ₅ is formed to cover the bottom and side surfaces of the first trench. In addition, a 10-nm thick Pt film 5 is formed to cover the bottom and side surfaces of this dielectric film 4 and fill the first trench.

[0129] An insulating interlayer 62 is formed on the insulating interlayer 61 including the first trench. Of this insulating interlayer 62 , substantially the same position as the first trench is selectively removed to form a second trench. The width in the channel length direction of this second trench is made smaller than that of the first trench. A 30-nm thick SBT ferroelectric film 6 is formed in the second trench. Accordingly, the ferroelectric film 6 is stacked in contact with the Pt film 5 , and the width in the channel length direction of this ferroelectric film 6 is smaller than that of the Pt film 5 .

[0130] An insulating interlayer 63 is formed on the insulating interlayer 62 including the ferroelectric film 6 . Of this insulating interlayer 63 , substantially the same position as the second trench is selectively removed to form a third trench. The width F, in the channel length direction of this third trench is made larger than that of the second trench. A 10-nm thick Pt film 7 is formed in the third trench. Accordingly, the Pt film 7 is stacked in contact with the ferroelectric film 6 , and the width of this Pt film 7 is larger than that of the ferroelectric film 6 .

[0131] Furthermore, an insulating interlayer 64 is formed on the insulating interlayer 63 including the Pt film 7 . Contact plugs 8 a to 8 c are formed in these insulating interlayers 61 to 64 . That is, the contact plug 8 a is formed by burying a metal in a contact hole reaching the source layer 1 a through the insulating interlayers 61 to 64 . The contact plug 8 b is formed by burying a metal in a contact hole reaching the drain layer 1 b through the insulating interlayers 61 to 64 . The contact plug 8 c is formed by burying a metal in a contact hole reaching the Pt film 7 through the insulating interlayer 64 . Also, trenches are formed in this insulating interlayer 64 so as to overlap these contact plugs 8 a to 8 c. In these trenches, lines 9 a to 9 c electrically connected to the contact plugs 8 a to 8 c are formed.

[0132] A method of fabricating the semiconductor device according to this embodiment will be described below with reference to sectional views shown in FIGS. 21A to 22 C.

[0133] First, as shown in FIG. 21A, a poly-Si layer 2 a and an SiN layer 2 b are sequentially stacked on the entire surface of an Si substrate 1 . These poly-Si layer 2 a and SiN layer 2 b are selectively left on the Si substrate 1 by patterning. A stacked structure of the selectively left SiN layer 2 b and poly-Si layer 2 a functions as a dummy gate (sacrificial structure) 2 .

[0134] This dummy gate 2 is used as a mask to form a source layer 1 a and a drain layer 1 b in the surface of the Si substrate 1 , by doping an impurity into the surface of the substrate 1 by ion implantation or the like. An insulating interlayer 61 is deposited on the Si substrate 1 in which the source layer 1 a and the drain layer 1 b are formed. The surface of this insulating interlayer 61 is planarized to expose the dummy gate 2 . In this planarization step, the SiN layer 2 b functions as a stopper.

[0135] As shown in FIG. 21 B, the dummy gate 2 is selectively removed while the insulating interlayer 61 is left behind. This step of removing the dummy gate 2 is done by using wet etching and CDE (Chemical Dry Etching). Since the removal is thus performed without using RIE, damage to the source layer 1 a and the drain layer 1 b is reduced. As a result of this removal of the dummy gate 2 , a first trench is formed inside the insulating interlayer 61 on a channel region 1 c sandwiched between the source layer 1 a and the drain layer 1 b.

[0136] As shown in FIG. 21C, a dielectric film 4 and a Pt film 5 are stacked in this order on the entire surface of the device. The dielectric film 4 and the Pt film 5 are formed by CVD. These dielectric film 4 and Pt film 5 are formed to be thin along the surface of the insulating interlayer 61 , and along the shape of the bottom and side surfaces of the first trench so as to cover this first trench with a substantially uniform film thickness. Accordingly, the dielectric film 4 and the Pt film 5 assume a sectional shape recessed at the depth of the trench. Also, the first trench has in the channel length direction a width larger than twice the sum of the film thicknesses of the dielectric film 4 and the Pt film 5 . That is, the upper surface of the Pt film 5 is lower than that of the insulating interlayer 61 .

[0137] As shown in FIG. 21 D, the upper surface of the device is planarized by using CMP. By this planarization, the Pt film 5 and the dielectric film 4 on the insulating interlayer 61 are removed in this order to expose the surface of the insulating interlayer 61 . CMP is continued even after the surface of the insulating interlayer 61 is thus exposed. CMP is terminated when the upper surface of the Pt film 5 formed at the lowest position in the trench is planarized and leveled with the surrounding insulating interlayer 61 . The result is a structure in which the bottom and side surfaces of the first trench inside the insulating interlayer 61 are covered with the dielectric film 4 , and the Pt film 5 is buried in the recess of the dielectric film 4 (the bottom and side surfaces of the recess are covered with the Pt film 5 ).

[0138] As shown in FIG. 22 A, an insulating interlayer 62 is deposited on the insulating interlayer 61 and the first trench. This insulating interlayer 62 is selectively removed to form, in substantially the same position as the first trench, a second trench having a width smaller than that of the first trench in the channel length direction. A ferroelectric film 6 is formed on the entire surface of the device including this second trench by CVD or the like. This ferroelectric film 6 is formed to be thin along the surface of the insulating interlayer 62 , and along the shape of the bottom and side surfaces of the second trench so as to cover this second trench with a substantially uniform film thickness. Accordingly, the ferroelectric film 6 has a sectional shape recessed at the depth of the second trench.

[0139] Next, the upper surface of the device is planarized by using CMP. By this planarization, the ferroelectric film 6 on the insulating interlayer 62 is removed to expose the insulting interlayer 62 . CMP is continued even after the surface of the insulating interlayer 62 is thus exposed. Consequently, the surface of this insulating interlayer 62 is removed by a predetermined film thickness and leveled with the surface of the ferroelectric film 6 . CMP is terminated in this stage. The result is a structure in which the ferroelectric film 6 is buried in the second trench.

[0140] As shown in FIG. 22 B, an insulating interlayer 63 is deposited on the insulating interlayer 62 including the ferroelectric film 6 . This insulating interlayer 63 is selectively removed to form, in substantially the same position as the second trench, a third trench having a width larger than that of the second trench in the channel length direction. A Pt film 7 is formed on the entire surface of the device including this third trench by CVD or the like. This Pt film 7 is formed to be thin along the surface of the insulating interlayer 63 , and along the shape of the bottom and side surfaces of the third trench so as to cover this third trench with a substantially uniform film thickness. Therefore, the Pt film 7 has a sectional shape recessed at the depth of the third trench.

[0141] Next, as shown in FIG. 22 C, the upper surface of the device is planarized by using CMP. By this planarization, the Pt film 7 on the insulating interlayer 63 is removed to expose the insulting interlayer 63 . CMP is continued even after the surface of the insulating interlayer 63 is thus exposed. Consequently, the surface of this insulating interlayer 63 is removed by a predetermined film thickness and leveled with the surface of the Pt film 7 . CMP is terminated in this stage. The result is a structure in which the Pt film 7 is buried in the third trench. Note that this third trench is wider than the second trench. Therefore, the Pt film 7 is formed to overlap the ferroelectric film 6 .

[0142] Furthermore, an insulating interlayer 64 is deposited on the entire device surface, and contact plugs 8 a to 8 c and lines 9 a to 9 c are formed. These steps are the same as in the first embodiment.

[0143] In this embodiment as described above, the Pt film 5 serving as a lower electrode, the dielectric film 4 , the ferroelectric film 6 , and the Pt film 7 are selectively formed using CMP. Accordingly, a gate capacitor structure can be formed without any patterning step using dry etching such as RIE. This can realize a gate capacitor structure not suffering plasma or chemical damage occurring when RIE or the like is used. Also, as in the first embodiment, the source layer 1 a and the drain layer 1 b are formed using the dummy gate 2 . This can reduce damage conventionally occurring on the source layer 1 a and the drain layer 1 b when the gate capacitor structure is patterned after the fabrication of the gate.

[0144] Furthermore, the Pt film 5 , the dielectric film 4 , the ferroelectric film 6 , and the Pt film 7 are sequentially formed in separate steps by CMP. Therefore, the areas of these dielectric film 4 , Pt film 5 , ferroelectric film 6 , and Pt film 7 are readily controllable by controlling the widths of trenches formed in insulating interlayers during the formation of these films 4 to 7 .

[0145] Sixth Embodiment

[0146] This embodiment relates to a modification of the fifth embodiment. This embodiment differs from the fifth embodiment in that the present invention is applied to an MFIS (electrode/ferroelectric film/dielectric film/semiconductor) structure.

[0147] FIG. 23 is a longitudinal sectional view showing the whole construction of a semiconductor device according to this embodiment. A difference of the arrangement of this semiconductor device shown in FIG. 23 from that shown in FIG. 20 resides in a gate capacitor structure. In FIG. 20, a gate capacitor structure is formed by a four-layered structure including the dielectric film 4 , the Pt film 5 , the ferroelectric film 6 , and the Pt film 7 . In FIG. 23, a gate capacitor structure is formed by a three-layered structure including a dielectric film 4 , a ferroelectric film 6 , and a Pt film 7 . The rest of the arrangement is the same as in FIG. 20 .

[0148] A method of fabricating the semiconductor device shown in FIG. 23 will be explained with reference to sectional views in FIGS. 24A to 25 B. In this method of fabricating the semiconductor device of this embodiment, the steps shown in FIGS. 21A and 21B of the fifth embodiment are similarly performed. A step shown in FIG. 24A follows the step shown in FIG. 21B .

[0149] As shown in FIG. 24 A, on the entire surface of the device including a first trench formed inside an insulating interlayer 61 , a dielectric film 4 is formed to be thin along the surface of the insulating interlayer 61 , and along the shape of the bottom and side surfaces of the first trench so as to cover this first trench with a substantially uniform film thickness, by using CVD or the like.

[0150] Next, as shown in FIG. 24 B, the upper surface of the device is planarized by using CMP. This CMP is continued until the insulting interlayer 61 is exposed and the surface of the insulating interlayer 61 is leveled with the surface of the dielectric film 4 on the first trench. This results in a structure in which the dielectric film 4 is selectively buried in the insulating interlayer 61 . An insulating interlayer 62 is deposited on the insulating interlayer 61 including the dielectric film 4 . This insulating interlayer 62 is selectively removed to form, in substantially the same position as the first trench, a second trench having a width smaller than that of the first trench in the channel length direction.

[0151] As shown in FIG. 24C, a ferroelectric film 6 is formed on the entire device surface including this second trench by CVD or the like. This ferroelectric film 6 is formed to be thin along the surface of the insulating interlayer 62 , and along the shape of the bottom and side surfaces of the second trench so as to cover this second trench with a substantially uniform film thickness. Therefore, the ferroelectric film 6 has a sectional shape recessed at the depth of the second trench.

[0152] As shown in FIG. 25 A, the upper surface of the device is planarized by CMP. As in the formation of the dielectric film 4 , the surface of the insulating layer 62 is exposed, and the ferroelectric film 6 having the surface on the same level as the surface of the insulating interlayer 62 is buried in the second trench. An insulating interlayer 63 is then formed on the insulating interlayer 62 including the ferroelectric film 6 . This insulating interlayer 63 is selectively removed to form, in substantially the same position as the second trench, a third trench having a width larger than that of the second trench in the channel length direction. As shown in FIG. 25B, a Pt film 7 is formed on the entire device surface including this third trench by CVD or the like. This Pt film 7 is formed to be thin along the surface of the insulating interlayer 63 , and along the shape of the bottom and side surfaces of the third trench so as to cover this third trench with a substantially uniform film thickness. Accordingly, the Pt film 7 has a sectional shape recessed at the depth of the third trench. In addition, the surfaces of this Pt film 7 and the insulating interlayer 63 are planarized by using CMP similar to the dielectric film 4 and the ferroelectric film 6 . Consequently, as shown in FIG. 23 , the Pt film 7 is selectively buried in the third trench in the insulating interlayer 63 .

[0153] Furthermore, an insulating interlayer 64 is deposited on the entire device surface, and contact plugs 8 a to 8 c and lines 9 a to 9 c are formed. These steps are the same as in the fifth embodiment. As a result, the semiconductor device shown in FIG. 23 is obtained.

[0154] In this embodiment as described above, even a semiconductor device including a ferroelectric gate capacitor with an MFIS (electrode/ferroelectric film/dielectric film/semiconductor) structure can achieve the same effects as the fifth embodiment.

[0155] Seventh Embodiment

[0156] This embodiment relates to a modification of the fifth embodiment. This embodiment differs from the fifth embodiment in that the present invention is applied to an MFS (electrode/ferroelectri