DETAILED DESCRIPTION

[0034] The present invention allows creation of a surface-area-enhanced ruthenium electrically conductive layer that has improved compatibility with high-dielectric-constant (“high-κ”) dielectric materials as compared to hemispherical-grain polysilicon (HSG).

[0035] The surface-area-enhanced electrically conductive layer is created by heating a film or layer comprising ruthenium oxide such as the layer 12 of FIG. 1 . The heating process, which may anneal the film or layer, is typically performed at low pressures of less than about 75 torr, desirably less than about 20 torr, and most desirably less than about 5 torr, and at high temperatures in the range of about 500 to 900° C., desirably about 750 to 850° C. The treatment is desirably performed in a non-oxidizing ambient. The heating process may be performed in a noble ambient, nitrogen ambient, or the like, or in a reducing ambient, which may reduce the temperature required. The heating process may also be performed in an electrically neutral environment, or with plasma or glow-discharge assistance or the like, which may also reduce the temperature required. Heating under relatively low pressure converts at least a portion of the ruthenium oxide to ruthenium and produces a rough surface on the layer. Temperature and pressure are preferably selected so as to enhance the ruthenium oxide to ruthenium conversion.

[0036] The surface-area-enhanced electrically conductive layer may be formed on a supporting structure 10 shown in partial cross-section in FIG. 1 . The supporting structure 10 may be any structure present in or on an integrated circuit during the fabrication thereof. In a typical example application, the supporting structure may be an electrically conductive material that will be in electrical contact with a capacitor plate formed by the surface-area-enhanced electrically conductive layer.

[0037] The ruthenium oxide layer 12 may be formed by any suitable method. Specific examples of such methods include chemical vapor deposition (CVD) or related process, or sputtering or related process, or the like. The ruthenium oxide layer may be stoichiometric ruthenium oxide (RuO ₂ ) or non-stoichiometric ruthenium oxide (RuO _x ).

[0038] If the layer 12 is formed via CVD, the deposition may be performed, for example, at pressures of 1-20 torr, desirably about 5 torr. The oxygen may be supplied in the form of O ₂ or other oxidizing gas, such as N ₂ O, NO, or ozone (O ₃ ). The oxygenating gas and a ruthenium precursor, and suitable diluent gasses, if desired, may be supplied at suitable flow rates, such as in the range of about 100-2000 sccm. Alternatively, the ruthenium precursor can be deliver by direct vaporization. Deposition may be performed for a time in the range of about 10 to 500 seconds, desirably for sufficient time and under sufficient conditions to deposit RuO _x or RuO ₂ to a thickness in the range of about 100 to 600 Angstroms.

[0039] The resulting ruthenium oxide layer 12 may optionally be pre-annealed, such as by rapid thermal anneal (RTA) in hydrogen or other suitable anneal environment at pressures in the range of 500 to 700 torr and temperatures in the range of 500 to 900° C. The pre-anneal stabilizes the film, promoting crystallization of ruthenium and ruthenium oxide phases.

[0040] The ruthenium oxide layer 12 , with or without a pre-anneal, is then treated at low pressure and high temperature as described above. The treatment may reduce the proportion of ruthenium oxide in the layer and increase the proportion of ruthenium. The ruthenium oxide in the ruthenium oxide layer 12 is partially or completely converted to ruthenium by the anneal, leaving an enhanced-surface-area layer 16 shown in the cross section of FIG. 2 . While the enhanced-surface-area layer 16 is referred to by separate reference character for convenience herein, it should be noted that the layer 16 is formed from the layer 12 , and is the same layer in that sense. FIG. 3 shows a partial plan view of the roughened ruthenium layer 16 of FIG. 2 . Although the example roughened ruthenium layer 16 shown in the figures is discontinuous, this is by way of example only and continuous films may also be produced. Increased thickness of the initial layer 12 tends to produce more continuous films, as does reduced temperature and increased pressure during the anneal and reduced anneal time.

[0041] The anneal may be performed in a noble, nitrogen, or reducing ambient or the like. As an additional example embodiment, an anneal may be performed in a nitrogen-supplying reducing ambient such as such as ammonia, nitrogen, a nitrogen and hydrogen mixture, and the like. The anneal parameters may be selected such that “nitrogen-passivated” ruthenium in the form of RuN _x is formed in the layer 16 , at least near the outermost surfaces thereof, passivating the layer 16 .

[0042] As another example alternative, nitride passivation may be used in the form of a post-anneal in a nitrogen-supplying reducing ambient.

[0043] As yet another variation, a desirably brief post-anneal in an oxidizing ambient such as oxygen or ozone may be performed on the already roughened layer 16 , to form “oxygen-passivated” ruthenium or ruthenium nitride in the outermost portions of the layer 16 (RuO _x N _y or RuO _x ), in order to reduce or prevent the ruthenium from later scavenging oxygen from a nearby dielectric material. The oxidizing post-anneal may optionally follow a nitride passivation post-anneal.

[0044] As indicated in FIG. 2 , the roughened ruthenium layer 16 , together with the supporting structure 10 if electrically conductive, may together constitute an enhanced-surface-area electrically conductive layer 26 compatible with high-dielectric-constant dielectric materials.

[0045] The layer 16 produced such as described above may also be used in cooperation with other layers. This may be useful in cases where the supporting structure 10 may not be electrically conductive or may be incompatible with high-dielectric-constant dielectric materials. In the discussion and claims herein, “on” used with respect to two layers, one “on” the other, means at least some contact between the layers, while “over” means the layers are in close proximity, but possibly with one or more additional intervening layers such that contact is not required. Neither “on” nor “over” implies any directionality as used herein.

[0046] As shown, for example, in FIG. 4, a layer 22 of material may be formed over the supporting structure 10 , with the roughened ruthenium layer 16 then formed on the layer 22 . The layer 22 may be an electrically conductive layer to electrically connect all portions of layer 16 . The layer 22 may also act as a barrier layer to prevent contact between high-dielectric-constant dielectrics, to be used for capacitor formation, and the supporting structure 10 . If the layer 22 is an electrically conductive layer, layer 22 together with layer 16 constitute an enhanced-surface-area electrically conductive layer 26 . Any compatible electrically conductive material may be used, such as Pt, Ir, IrO _x , Rh, RuSi _x , and SrRuO _x and alloys thereof as well as RuSiO _x and RuSiN _x , for example.

[0047] Alternatively, as shown for example in FIG. 5, a layer 24 of electrically conductive material may be formed conformally over the layer 16 and over the supporting structure 10 . The layer 24 , together with the layer 16 , then constitutes an enhanced-surface-area electrically conductive layer 26 . As with the layer 22 , the layer 24 may function to electrically connect all portions of layer 16 , and may also function as a barrier layer to prevent contact between high-dielectric-constant dielectrics and the supporting structure 10 . Examples of such electrically conductive materials include the materials listed in the preceding paragraph. Ruthenium oxide is a desirable material because of compatibility with the underlying ruthenium layer 16 .

[0048] As described by way of example above with reference to FIGS. 3 - 6 , the supporting structure 10 and/or one or more layers above or below the layer 16 (or both) may be electrically conductive and may be employed as needed to obtain conductivity and other desired properties. The resulting enhanced-surface-area electrically conductive layer 26 , shown by way of example in FIGS. 3, 5 , and 6 , is represented generically as layer 26 in FIG. 6 . To form a capacitor with the enhanced-surface-area electrically conductive layer 26 , a layer 28 of dielectric material, most desirably a high-dielectric-constant dielectric material (generally any dielectric with a dielectric constant of at least 9 ), such as tantalum pentoxide (Ta ₂ O ₅ ), may be formed conformally over the enhanced-surface-area electrically conductive layer, as shown in FIG. 6 . Other high-constant dielectrics may also be employed, such as barium strontium titanium oxide (Ba,Sr)TiO ₃ , lead zirconium titanium oxide Pb(Zr,Ti)O ₃ , and strontium bismuth tantalum oxide (SrBi ₂ Ta ₂ O ₉ ), for example. The layer 28 is desirably sufficiently thin and conforming to provide an at least somewhat enhanced surface area on the surface away from the layer 26 .

[0049] An electrically conductive layer 30 may then be formed conformally over the dielectric layer 28 , as shown in FIG. 7 . The surface of layer 30 uppermost in the figure is not shown because the layer may generally be of any thickness sufficiently thick to insure continuity of the layer and sufficiently thin to fit within the overall volume allotted to the capacitor. As shown in FIG. 7 , the surface of layer 30 next to the dielectric layer 28 desirably conforms to the enhanced surface area of the dielectric layer 28 , providing an enhanced surface area for the electrically conductive layer 30 as well. The two electrically conductive layers, layers 26 and 30 , form the two plates of a capacitor. Both plates desirably have enhanced surface area relative to the area occupied by the capacitor.

[0050] Application of the plate structure shown in FIG. 7 to a container capacitor is illustrated in the cross-section of a container capacitor shown in FIG. 8A . The supporting structure 10 may be an electrically conductive plug of polysilicon or other electrically conductive material formed at the bottom of an opening in a dielectric material 32 such as borophosphosilicate glass (BPSG). The lower end of the plug typically electrically contacts a circuit element such as a transistor gate (not shown). At the sides of the cylindrical container, the BPSG itself functions a supporting structure for the capacitor plate structure. The relative thinness of the capacitor structure provided by the layer structure of FIG. 7 maximizes the capacitor plate surface area in the container capacitor of FIG. 8 A, particularly for the inner (upper) electrode, the surface area of which decreases most rapidly with increasing thickness of the layer structure. The use of the enhanced-surface-area ruthenium electrically conductive layer thus provides improved capacitance in a given area.

[0051] Application of the plate structure shown in FIG. 7 to a stud capacitor is illustrated in the cross-section of a stud capacitor shown in FIG. 8B . The supporting structure 10 includes a plug 25 that extends from a surface 27 and the layers 26 , 28 , 30 are formed conformally on the plug 25 .

[0052] In a specific example, ruthenium oxide was deposited on substrates of BPSG to a thickness of about 600 Angstroms by CVD. The ruthenium oxide layers were pre-annealed in nitrogen for one minute at 800° C. and 600 torr, then annealed at 800° C. in nitrogen for varying times and at varying pressures. Such a pre-anneal can be omitted.

[0053] On SEM examination, layers annealed for eight minutes at 4.5 torr showed marked surface roughness with mean grain size of about 100 Angstroms or larger, with good uniformity over the substrate surface. Layers annealed for eight minutes at 60 torr showed some surface roughness with a mean grain approaching 100 Angstroms, but with generally less roughness than at 4.5 torr. Layers annealed for eight minutes at 600 torr showed generally still less roughness and still smaller grain sizes than at 60 torr. Layers annealed for two minutes at 4.5 torr also showed a marked surface roughness, with possibly slightly less uniformity over the substrate surface than those annealed for eight minutes. X-ray diffraction studies of the annealed layers showed ruthenium as the primary constituent but the Ru/RuO ₂ ratio varied with processing conditions.

[0054] Superior capacitors including metal-insulator-metal (MIM) capacitors can be obtained using a tungsten nitride layer as an electrode. The tungsten nitride layer can be formed by reactive sputtering of a tungsten target in a nitrogen containing ambient, or by a chemical vapor deposition process (CVD) such as a plasma enhanced CVD (PECVD), a metallo-organic CVD (MOCVD) process, atomic layer deposition (ALD), or other process. The tungsten nitride layer is conveniently formed using a thermal CVD process using tungsten fluoride (WF ₆ ) and ammonia (NH ₃ ) as precursors, and a 300 Angstrom thick layer can be formed using such a process in about 1-3 minutes. The thickness of the tungsten nitride layer can be varied but typically the thickness is in the range of 100-1000 Angstroms.

[0055] As deposited, the tungsten nitride layer can contain a mixture of a stable tungsten nitride compound W ₂ N and a metastable tungsten nitride compound WN. The metastable compound WN can be converted to the stable tungsten nitride compound W ₂ N in a rapid thermal process (RTP) in which the temperature of the tungsten nitride layer is rapidly raised to an anneal temperature in the range of 600-800 C. and held at the anneal temperature for about 60 seconds. Typically, the temperature of the tungsten nitride layer is ramped up to and down from an anneal temperature of 700 C. in less than about 30 seconds. Such an anneal process is typically performed before a dielectric layer and a second electrode are formed on the tungsten nitride layer so that a capacitor structure is otherwise complete. The metastable compound WN may include defects and may be preferentially oxidized during deposition of dielectric materials such as Ta ₂ O ₅ and subsequent annealing processes. Therefore, the capacitance of a capacitor formed is without an anneal process tends to be low. In addition, the presence of defects tends to increase leakage currents. In a completed capacitor, the anneal process tends to increase capacitance by about 20% with respect to a capacitor without annealing and to reduce leakage currents that occur when voltages are applied to the electrodes.

[0056] A dielectric layer consisting of any of various dielectric materials is formed on the tungsten nitride layer. Suitable dielectric materials include high-dielectric-constant materials such as tantalum pentoxide (Ta ₂ O ₅ ), doped Ta ₂ O ₅ such as Ti-doped Ta ₂ O ₅ , barium strontium titanium oxide (Ba,Sr)TiO ₃ , lead zirconium titanium oxide Pb(Zr,Ti)O ₃ , strontium bismuth tantalum oxide (SrBi ₂ Ta ₂ O ₉ ), BaTiO ₃ , SrTiO ₃ , Pb(Zr,Ti)O ₃ , SrBi ₂ Ta ₂ O ₉ , SrBi ₂ Nb ₂ O ₉ , SrBi ₂ (Nb,Ta) ₂ O ₉ , (Pb,La)(Zr,Ti)O ₃ , Al ₂ O ₃ , ZrO ₂ , HfO ₂ , and SiO _x N _y . For Ta ₂ O ₅ , formation of a stoichiometric compound is preferred so that the Ta ₂ O ₅ layer is not a tantalum rich layer, because tantalum rich Ta ₂ O ₅ layers tend to be conducting, not insulating. Tantalum pentoxide dielectric layers are preferred in some applications because of its large dielectric constant and its stability. However, tantalum pentoxide is typically formed using a MOCVD process in an oxidizing ambient such as an oxygen, ozone, or N ₂ O ambient. While many electrode layer materials cannot be exposed to oxidizing ambients, tungsten nitride is relatively unaffected by such ambients and therefore facilitates the use of tantalum pentoxide dielectric layers.

[0057] An electrode layer of tungsten nitride or other conducting material is formed on the dielectric layer and serves as a top electrode for the capacitor. Other suitable conducting materials include TiN, TiON, WN _x , TaN, Ta, Pt, Rh, Pt—Rh, Pt—RhO _x , Ru, RuO _x , Ir, IrO _x , Pt—Ru, Pt—RuO _x , Pt—Ir, Pt—IrO _x , SrRuO ₃ , Au, Pd, Al, Mo, Ag, polysilicon, and alloys thereof. These electrode materials can be formed by various processes. For example, ruthenium and platinum/rhodium are conveniently formed using a CVD process. After the dielectric layer and the electrode layers are formed, the capacitor is annealed as described above.

[0058] FIGS. 9 A- 9 C illustrate several example capacitor geometries that include tungsten nitride electrodes. Referring to FIG. 9A, a plate capacitor 51 is formed on a surface of a substrate 53 . The substrate 53 can be any of various substrate materials including GaAs, 10 silicon, or BPSG. The capacitor 51 includes a first electrode 55 , a second electrode 57 , and a dielectric layer 59 . In a representative example, the first electrode 55 is a tungsten nitride layer, the dielectric layer 58 is a Ta ₂ O ₅ layer, the second electrode is a TiN layer, and the substrate 53 is BPSG.

[0059] When voltages are applied to electrodes of a capacitor such as the capacitor 51 , some electrical current flows between the electrodes. This current is generally undesirable and is referred to as a “leakage” current. Plate capacitors having electrodes of tungsten nitride have leakage currents of as little as about 20 nA/cm ² , or as low as about 5 nA/cm ² for capacitors having dielectric layers 100 Angstroms thick and with an applied voltage of 1 V.

[0060] With reference to FIG. 9B, a container capacitor 61 is formed in an etched recess 62 in a substrate 63 . A tungsten nitride electrode layer 65 covers a bottom surface 66 and a side surface 67 of the recess 62 . A Ta ₂ O ₅ dielectric layer 69 covers the electrode layer 65 , substantially filling the recess 62 and a tungsten nitride electrode layer 71 (or other conductive layer) covers the dielectric layer 69 . The dimensions of the recess 62 are selected to provide a desired capacitance, and can be selected in conjunction with a minimum feature size for other circuit elements that are formed on the substrate 63 . In a representative example, the recess 62 has a diameter D of 200 nm and a depth Z of 1000 nm. For these dimensions, the tungsten nitride layer is preferably about 300 Angstroms (30 nm) thick. Tungsten nitride layers thinner than about 100 Angstroms (10 nm) tend to have voids. Because of these voids, such layers do not act as continuous electrodes, reducing the capacitance of the capacitor 61 . Tungsten nitride layers thicker than about 1000 Angstroms (100 nm) tend to occupy too much of the volume of the recess 62 , also limiting the capacitance of the capacitor 61 . For container capacitors formed in larger recesses, thicker tungsten nitride layers can be used without sacrificing too much capacitance.

[0061] The recess 62 is generally formed in the substrate 63 with an etching process. If the substrate 63 is BPSG, the recess 62 can be formed with a dry etch process such as plasma etching. While other etching processes are possible, because the recess 62 is deeper than wide, a selected etch process is preferably anisotropic.

[0062] Referring to FIG. 9C, a stud capacitor 71 is formed on a plug 73 that extends from a surface 75 of a substrate 77 . A tungsten nitride electrode layer 79 is formed on the plug 73 and is covered with a dielectric layer 81 and an electrode layer 83 . The dielectric layer 81 and the electrode layer can be formed of any of the materials mentioned above. Representative materials are Ta ₂ O ₅ and TiN for the dielectric layer 81 and the electrode layer 83 , respectively. The plug 73 may be an electrically conductive plug of polysilicon or other electrically conductive material formed in a recess in the substrate 77 such as a borophosphosilicate glass (BPSG). The lower end of the plug typically electrically contacts a circuit element such as a transistor gate (not shown).

[0063] In the above examples, a tungsten nitride layer is deposited directly on a substrate such as BPSG. Alternatively, a tungsten nitride layer can be formed or deposited on a titanium nitride (TiN) adhesion layer, or other adhesion layer, to improve the bonding of the tungsten nitride layer to the substrate.

[0064] Variations within the scope and spirit of the disclosure above will be apparent to those of ordinary skill in the art. For example, the enhanced-surface-area layers can be used in ferroelectric memories to improve storage capacity. The scope of coverage is accordingly defined not by the particular example embodiments and variations explicitly described above, but by the claims below.