DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] Referring now to the figures of the drawing in detail and first, particularly, to FIG. 2 thereof, there is shown a simplified sectional view of a first embodiment of a vertical non-volatile semiconductor memory cell.

[0033] FIG. 2 shows a semiconductor substrate 20 that is composed of an n type doped base layer 1 and that has a p doped semiconductor layer 2 deposited epitaxially thereon, with n ⁺ regions 3 formed therein. The semiconductor substrate 1 is preferably composed of Si. However, it can also have an SiGe, SiC, GaAs or some other compound conductor, and can be embedded in a multilayer structure made of isolating, semiconducting and conductive layers, for example, in the manner of SOS and SOI. In the same way, reverse doping for the regions 1 , 2 and 3 can also be used, as a result of which a p-n-p layer sequence is obtained. In the same way, the semiconductor layer 2 can also be formed by means of diffusion or by some other means.

[0034] A depression is formed in the semiconductor substrate 20 , extending as far as the base layer 1 , using an auxiliary layer 4 and a mask layer (not illustrated). The lower part of this depression constitutes the later trench extension 5 ′, while an upper part forms the trench 5 for the actual vertical non-volatile semiconductor memory cell.

[0035] The trench extension 5 ′ is coated on its surface with a third dielectric layer 6 which is preferably composed of an ONO layer sequence (oxide/nitride/oxide). The remaining space in the trench extension 5 ′ is filled with a filler material 7 , which is preferably composed of polysilicon. However, it can also be composed of a silicide, for example MoSi, WSi etc., or have an electrically isolating material. The third dielectric layer 6 and the filler material 7 are preferably formed in the entire trench 5 and 5 ′, and subsequently countersunk by means of a suitable etching method to a depth just below the p type doped layer 2 which forms a channel layer. A first dielectric layer 8 , which acts as a tunnel layer of the vertical non-volatile semiconductor memory cell, is subsequently formed on the surface of the trench 5 , for example, by means of thermal oxidation. This tunnel layer 8 is preferably composed of SiO ₂ , but other suitable thin tunnel layers can also be used.

[0036] In order to improve the isolation of the trench extension 5 ′, it is possible to provide reinforcement (not illustrated) of the first dielectric layer 8 , before or during the production of the first dielectric layer on the upper edge of the filler material 7 and the directly adjacent wall of the trench 5 , for example as far as the upper edge of the layer 1 . This reinforcement can advantageously be obtained using, for example, different oxidation rates of the filler material 7 and of the semiconductor layers 1 and 2 . Likewise, suitable combinations of deposition and etching processes, in particular using an anisotropy, are possible in order to manufacture the reinforcement.

[0037] FIG. 2 shows that the trench 5 is also filled with a charge storage layer 9 composed, for example, of polysilicon or a silicide, and is subsequently etched, or only the side walls of the trench 5 are coated, as a result of which, a control layer trench 5 ″ is formed. According to FIG. 2 , this control layer trench 5 ″ extends to the bottom of the trench 5 . A second dielectric layer 10 , which is in turn composed, for example, of an ONO layer sequence, is formed on the side walls of the control layer trench 5 ″. However, in order to increase a coupling factor of the non-volatile semiconductor memory cell, this second dielectric layer 10 can also be composed of a dielectric with a high relative dielectric constant ε _r , in which in particular metal oxides can be used. Such metal oxides, which can be used for the second dielectric layer 10 are, for example, TiO ₂ , Wo _x , Al ₂ O ₃ etc.

[0038] The control layer trench 5 ″ is subsequently filled with an electrically conductive control layer 11 or control filler layer 11 ′, which forms a control gate terminal of the non-volatile semiconductor memory cell. This control layer 11 or control filler layer 11 ′ is composed, for example, of highly doped polysilicon, but can also be composed of any other electrically conductive material, for example silicide. Furthermore, a material which is different from the surface material 11 can be used for the control filler layer 11 ′ located in the control layer trench 5 ″, as a result of which optimum filling, and thus optimum formation of a contact, can be realized, in particular with very fine structures. The filling of the control layer trench 5 ″ can also be constructed from more than two layers in the same way.

[0039] In this way, a vertical non-volatile semiconductor memory cell is obtained whose channel length is determined essentially by the thickness of the layer 2 . By using the base layer 1 , space can be saved, to be used for a contact, in which case an additional topological structure on the surface is also avoided by moving the charge storage layer 9 to the trench, and a shrink capability is thus improved. However, in particular as a result of the trench extension 5 ′ with its additional dielectric layer 6 and the filler material 7 located in it, the data retention properties of the semiconductor memory cell are enhanced, which improves in particular what is referred to as the “retention time”. Furthermore, such a non-volatile semiconductor memory cell can be manufactured at low cost because the formation of such deep trenches or depressions with the associated dielectric layer and the filler material from a multiplicity of standard processes is already known, and no additional costs are therefore incurred. A detailed description of this advantage is given below with reference to FIG. 6 .

[0040] FIG. 3 shows simplified sectional view of a second embodiment of a vertical non-volatile semiconductor memory cell. Identical reference symbols indicate identical layers or elements and a repeated description is dispensed with below.

[0041] FIG. 3 shows that the essential difference between this second exemplary embodiment and the semiconductor memory cell shown in FIG. 2 is that the control layer trench 5 ″ is countersunk only partially into the charge storage layer 9 , as a result of which improved charge retention properties and programming properties can be obtained for specific materials. In the extreme case (not illustrated), the control layer trench 5 ″ can be virtually eliminated here, as a result of which the second dielectric layer 10 extends completely parallel to the surface of the semiconductor substrate, and the topological properties are greatly improved. In particular in the case of materials, which are highly topologically dependent, this results in a significant simplification and improvement of the manufacturing process, but generally worsens a coupling factor.

[0042] FIG. 4 shows a simplified sectional view of a third exemplary embodiment of a vertical non-volatile semiconductor memory cell. Identical reference symbols again designate identical layers or elements and a repeated description is dispensed with below.

[0043] FIG. 4 shows that the first dielectric layer 8 , which is present on the bottom can now be dispensed with and a direct contact can be formed between the filler material 7 and the charge storage layer 9 . If appropriate materials, for example highly doped polysilicon (conductive), are used for both the charge storage layer 9 and for the filler material 7 , the coupling factor of the semiconductor memory cell can thus be significantly improved.

[0044] However, the control layer trench 5 ″ can also additionally extend into the filler material 7 , as a result of which a coupling factor can be further optimized, and furthermore an etching process window for forming the control layer trench 5 ″ can be made significantly less critical. The manufacturing costs can thus be reduced further. Nevertheless, in particular by using the third dielectric layer 6 , the data retention properties of the semiconductor memory cell can continue to be improved, in contrast to conventional vertical semiconductor memory cells.

[0045] FIG. 5 shows a simplified sectional view of a fourth exemplary embodiment of a vertical non-volatile semiconductor memory. Identical reference symbols again designate identical layers and a repeated description is dispensed with below.

[0046] FIG. 5 shows that the control layer trench 5 ″ extends from the surface of the semiconductor substrate 20 through the charge storage layer 9 and the filler material 7 into the substrate or the base layer 1 . In such a semiconductor memory cell, a particularly less critical etching process window for the control layer trench 5 ″ is obtained, as a result of which the manufacturing costs can be reduced further. Furthermore, if suitable materials are used a coupling factor of the semiconductor memory cell can be improved further because the surface between the control layer 11 and the control filler layer 11 ′ used in the control layer trench 5 ″ is increased further. In particular when highly doped polysilicon is used as the charge storage layer 9 and as a filler material 7 , these then act together as a charge storage layer, in which case in particular the data retention properties and thus the “retention time” of the semiconductor memory cell are also improved by virtue of the third dielectric layer 6 .

[0047] According to FIGS. 2 to 5 , an auxiliary layer 4 was used for masking in each case; however, it can also be dispensed with. In addition, a non-volatile charge storage layer (for example nitride) or some other charge-storing material can also be used instead of an electrically conductive charge storage layer 9 (highly doped polysilicon).

[0048] A vertical non-volatile semiconductor memory cell with an associated selector transistor as an EEPROM memory cell in a preferred fifth exemplary embodiment is described below.

[0049] FIG. 6 shows a simplified sectional view of the fifth exemplary embodiment. Identical reference symbols again designate identical layers or elements and a repeated description is dispensed with below. FIG. 6 shows that the vertical non-volatile semiconductor memory cell is integrated directly into a DRAM process, as a result of which the manufacturing costs can be reduced further on the basis of already known process sequences, and the non-volatile semiconductor memory cell can be manufactured in what is referred to as an embedded DRAM process. To be more precise, in this way both DRAM memory cells and non-volatile vertical semiconductor memory cells with improved data retention properties can be manufactured particularly cost-effectively on the same wafer.

[0050] FIG. 6 shows that the EEPROM semiconductor memory cell has a very similar structure to a conventional DRAM semiconductor memory cell with a trench capacitor. To be more precise, the same processes as for the trench capacitor in a DRAM memory cell are used to form the trench extension 5 ′ and the trench 5 ′. A deep trench is first made in the semiconductor substrate 20 and then the trench is at least partially filled with a dielectric layer 6 and an electrically conductive filler material 7 . The deep trench here can have a bottle shape (not illustrated) and also a buried plate (not illustrated), which is necessary in DRAM memory cells.

[0051] Formation of the deep trench 5 or 5 ′, of the third dielectric layer 6 and of the filler material 7 and the countersinking of the filler material 7 and removal of the third dielectric layer 6 in the upper region of the trench thus corresponds to the corresponding steps during the manufacture of a DRAM trench capacitor. A detailed description is not given below because the steps are sufficiently known to the person skilled in the art.

[0052] However, with the method according to the invention for manufacturing the vertical non-volatile semiconductor memory cell, instead of producing the isolation collar in the DRAM process the first dielectric layer 8 is preferably formed as an SiO _x tunnel layer on the trench walls of the trench 5 and is subsequently filled with a charge storage layer 9 , which is preferably composed of highly doped polysilicon. The highly doped polysilicon layer 9 lies here directly on the (possibly highly doped) polysilicon layer, serving as the filler material 7 , of the trench extension 5 ′, resulting in a virtually enlarged charge storage layer 9 or 7 . Subsequently, a control layer trench 5 ″ is preferably formed at least partially in the charge storage layer 9 by means of an anisotropic etching process. The control layer trench 5 ′ extends, according to FIG. 6 , into the filler material 7 . The second dielectric layer 10 is then formed in the control layer trench 5 ″, in which case an ONO layer sequence or a dielectric with a high relative dielectric constant ε _r is preferably used. A (filler) control layer 11 ′ is then formed in the remaining part of the control layer trench 5 ″ and is preferably composed of an electrically conductive polysilicon.

[0053] A control gate layer 11 is located on the surface of the substrate and is in contact with the (filler) control layer 11 ′ in order to form a control gate CG of the non-volatile semiconductor memory cell. In order to avoid undesired leakage currents at the surface, an isolation collar 12 is located at an upper region of the trench 5 . The further elements, for example such as the selector transistor AT composed of a gate 14 of an isolation trench 15 , and drain and source regions 3 and 16 with a contact terminal 17 are in turn formed with a conventional DRAM process. In the same way, respectively adjacent vertical non-volatile semiconductor memory cells (not illustrated) are separated from one another by a shallow trench isolation 13 (STI) present in the DRAM process.

[0054] As in the exemplary embodiments shown in FIGS. 2 - 5 , the control layer trench 5 ″ can be formed to different depths, as a result of which in particular an etching process window for this trench is made significantly less critical. The essential advantage of this fifth exemplary embodiment is that a DRAM process, which is present in any case can be used to form trench capacitors for the vertical non-volatile semiconductor memory cell according to the invention, in which case improved data retention properties are obtained. Furthermore, this permits an embedded DRAM process in which both non-volatile and dynamic semiconductor memory cells can be formed in the same semiconductor substrate. This allows new circuits to be formed in particular in smart cards and chip cards.

[0055] FIG. 7 shows an equivalent circuit diagram of the EEPROM semiconductor memory cell illustrated in FIG. 6 . The circuit diagram will be described below in order to clarify the influence of the respective layers on a coupling factor.

[0056] FIG. 7 shows the indices of the capacitors designate the respective layers or regions of FIG. 6 , which generate these capacitances. Accordingly, the selector transistor AT has parasitic capacitances C _14/16 and C _14/3 to the drain and source regions 16 and 3 . In addition, there are parasitic capacitances C _2/16 , C _2/14 , C _2/9 and C _2/3 to the epitaxially grown p type layer 2 (bulk), which serves as a channel layer. The actual non-volatile vertical semiconductor memory cell has parasitic capacitances C _3/11 and C _1/11 from the control layer 11 or 11 ′ to the n ⁺ type region 3 and to the n type base layer 1 . There is a further parasitic capacitance C _14/11 between the control layer 11 and the control gate layer 14 of the selector transistor, the capacitance C _7/1 constituting a capacitance between the filler material and the n type base layer 1 . When an optimum isolating layer is used between the filler material 7 and the charge storage layer 9 there is additionally the capacitance C _9/7 between these two materials.

[0057] In order to obtain the highest possible coupling factor, in particular, a capacitance C _11/9 between the control layer 11 or 11 ′ and the charge storage layer 9 must be as large as possible, or the entire capacitance of the remaining capacitors must be as low as possible. Given knowledge of this relationship it is possible to use suitable materials for the respective layers and trenches and to vary the depth of the control layer trench 5 ″ in order to set an optimum or maximum coupling value or coupling factor. In this way, in addition to the improved data retention properties, particularly favorable programming voltages can also be obtained.