DETAILED DESCRIPTION

[0022] Generally, the present invention provides semiconductor package support elements 42 (FIG. 2a and 2B) having one or more covered reject die sites 36 (FIGS. 2A-2E) and methods for making semiconductor packages 70, 72 from the same (FIGS. 3A and 3B).

[0023] More specifically, with reference to FIGS. 2A-2C, an embodiment of the support element 42 of the present invention includes multiple substrates 56. Each substrate 56 is a segment of the support element 42 and will subsequently be separated from the adjacent substrates 56 to form a semiconductor package 70 (FIGS. 2A and 3A). In the illustrative embodiment there are 18 substrates 56 on the support element 42 (FIGS. 2A and 2B). However, this number is merely exemplary and the support element 42 may include a fewer or greater number of substrates 56. The substrates 56 are typically positioned side-by-side and are integrally connected. As stated above, the support element 42 facilitates the fabrication process in that different operations, such as die attach and wire bonding, can be performed at the same time on multiple substrates 56.

[0024] The substrates 56 of the support element 42 preferably comprise electrically insulating materials, such as organic polymer resins reinforced with glass fibers, metals, epoxy resins (e.g., FR-4 and FR-5), ceramics, and other such materials used in electronic applications. The support element 42 (thus, the substrates 56) is formed to be of desired dimensions as known to those persons skilled in the art (such as a desired thickness of from about 0.2 mm to about 1.6 mm), depending upon the type of semiconductor packages to be formed therefrom.

[0025] Each substrate 56 of the support element 42 further includes a first planar surface 44 (FIG. 2A) and a second planar surface 46 (FIG. 2B). In FIG. 2C a single substrate 56 of support element 42 is illustrated in greater detail. Each substrate 56 further includes conductors 47. The conductors 47 are preferably patterned on the first surface 44 of each substrate 56. Conductors 47 preferably comprise a layer of conductive metal, such as copper, titanium, tungsten, gold or nickel.

[0026] Each substrate 56 preferably further includes wire bonding pads 52 to facilitate the wire bonding process. Each substrate 56 includes a substantially planar die attach area on the second surface 46 upon which a die 74 (FIG. 3A) is attached to the substrate. The die attach area of each substrate 56 comprises either an “operational” or “functional die site” 50 or a “defective” or “reject die site” 36 (FIGS. 2A and 2B). As discussed above, substrates 56 of a support element may be defective (i.e., the substrate may have a “reject die site” 36) for a variety of reasons, such as faulty electrical circuitry of the substrates.

[0027] Each substrate 56 of the support element 42 further includes a wire bond slot 64. The wire bond slot 64 extends from the first surface 44, through the substrate 56 to the second surface 46. Although shown rectangular in shape, wire bond slots 64 may be of any suitable size and shape, as is known to those persons skilled in the art. The wire bond slots 64 provide access for bonding wires 80 (see FIGS. 3A and 3B). The bonding wires 80 connect the die 74 circuitry to the corresponding substrate 56 circuitry (later in the semiconductor package fabrication process).

[0028] Each reject die site 36 of the support element 42 includes a cover member 48 (cover members 48 are shown with cross-hatch in FIGS. 2A-2E). The cover member 48 is preferably attached to the reject die site 36 so as to cover from about 70% to about 100% of the corresponding wire bond slot 64 on the die site. Preferred ranges of coverage of the wire bond slot 64 are discussed below with reference to FIGS. 2C-2E. The wire bond slot 64 is covered to prevent contamination through the slot during the encapsulation process. (The support member 42, wire bond slots 64, and die sites 36, 50 are illustrated in FIGS. 2A-2E prior to formation of a solder mask, solder balls or an encapsulation resin 92 that complete formation of the semiconductor packages 70, 72. The semiconductor packages 70, 72 are shown in complete form in FIGS. 3A and 3B.) Cover member 48 may comprise any sufficiently rigid material that can be adhered to first surface 44 of the support element 42. Of course, cover member 48 preferably will not comprise a material that would contaminate or otherwise negatively impact the operation of a completed semiconductor package 70 (FIG. 3A). The cover member 48 material must be able to withstand encapsulation pressures, typically from about 100 psi to about 1800 psi. For example, in one embodiment of support element 42, cover member 48 comprises pressure-sensitive (preferably one-sided) tape, such as KAPTON™ tape (available from Precision PCB Services, Inc., of Santa Clara, Calif.). In an alternative embodiment of the support element 42, cover member 48 comprises temperature-sensitive tape, such as ABLESTIK™ tape, (SKU No. RP444-1 4 available from National Starch and Chemical Co., of Bridgewater, N.J.). In yet another embodiment of the support element 42 of the present invention, the cover member 48 comprises a non-functional or reject die.

[0029] Cover member 48 is preferably relatively specifically attached to cover A majority of the wire bond slot 64 opening. That is, cover member 48 is attached to cover a sufficient portion of the wire bond slot 64 opening so as to eliminate bleeding or flashing during encapsulation but not so much as to cause a negative pressure zone on the substrate 56 during the encapsulation process.

[0030] The percentage of coverage of the wire bond slot 64 with the cover member 48 may vary depending upon the encapsulation material to be used and the width of the wire bond slot 64. Nonetheless, it has been discovered that for most conventional encapsulation materials and convention slot widths, the cover member 48 should cover from about 70% to about 100% of the wire bond slot 64 opening. It has been discovered that when a cover member 48 (comprising tape or other suitable material as discussed above) is attached to a reject die site 36 to completely cover (i.e., cover 100% of) wire bond slot 64 (as shown in FIG. 2D), a negative pressure on the first surface 44 of the substrate 56 may occur during the encapsulation process. A negative pressure may cause undesirable bending or bowing of the substrate 56 near or at the edges of the wire bond slot 64. It has also been discovered that 100% coverage of the wire bond slot 64 opening may work if the cover member material and the adhesive for attaching the cover member to the substrate 56 are sufficiently strong so as to withstand the encapsulation process pressures. It is possible, however, that with some substrate materials, the substrate 56 is deformed beyond acceptable limitations due to the pressures built up when the wire bond slot 64 is covered completely.

[0031] The optimum percentage of coverage of the wire bond slot 64 with the cover member 48 will necessarily depend on the encapsulation material to be used and the wire bond slot 64 width. Nonetheless, it has also been discovered that when a cover member 48 is attached to a reject die site 36 to cover just a major portion of the bonding slot 64 (i.e., from about 70% to about 98% or, more preferably from about 80% to about 95%, and most preferably about 90% coverage of the wire bond slot 64 opening) (see FIG. 2C) encapsulation material bleeding is virtually or completely eliminated. Furthermore, a negative pressure zone at the substrate 56 is not created during encapsulation.

[0032] It has also been discovered that when a cover member 48 is attached to a reject die site 36 to cover a minor portion of the bonding slot 64 (i.e., less that about 65% of the wire bond slot 64 opening (see FIG. 2E) bleeding or flashing often occurs. On the other hand, 65% coverage is better than no coverage of the wire bond slot 64 opening. Further, bleeding is most frequently a problem when the encapsulation material enters the solder ball attachment pad area of the semiconductor package 70 (FIG. 3A). Semiconductor packages having smaller pitches and less space between the solder ball attachment pads are more susceptible to contamination from encapsulation bleed than are semiconductor packages having wider pitches or greater spaces between the ball attachment pads.

[0033] Each functional die site 50 of support element 42 (during manufacture of the semiconductor package 70, FIG. 3A) will have a die (not shown in FIGS. 2A-2E) attached thereto, to cover wire bond slot 64. The support element 42 illustrated in FIGS. 2A and 2B is shown prior to attachment of a die. Functional or operational die (not shown) are attached to functional die sites 50 only.

[0034] As shown in FIG. 2A, the support element 42 of the present invention may also include one or more indexing openings 58 formed through one or more of the substrates 56, proximate longitudinal edges of the support element. The indexing openings 58 permit support element 42 to be handled by automated transfer mechanisms associated with chip bonders, wire bonders, molds, trim machinery, etc. Additionally, support element 42 may include separation openings 60 to facilitate singulation of individual substrates 56 from support element 42 after formation of the semiconductor packages 70, 72 (FIGS. 3A and 3B).

[0035] As shown in FIG. 2C, the substrate 56 may also include a triangular material segment 66 to function as a pin #1 indicator and a circular metal segment 68 to function as an alignment fiducial. Both segments 66, 68 are preferably formed on the first surface 44 of support element 42 at each substrate. The metal segments 66, 68 may comprise the same metal as the conductors 47.

[0036] Prior to the die attachment process, defect substrates 12 (and thus reject die sites are detected and marked using conventional methods known to those skilled in the art. Defective substrates 12 are then marked for identification of reject die sites thereon. A simple pen marking on the defective substrates 12 may be used to identify the reject die sites 36. Other methods of marking or identifying defect substrates 12 as known to those skilled in the art may be used to identify the defective substrates 12.

[0037] With reference to the process flow chart illustrated in FIG. 4, a cover member 48 may be attached to the reject die sites at a number of different stages during the semiconductor package manufacture process. The cover member 48, however, should be attached prior to the encapsulation process (Step 6 in FIG. 4). For example, according to a first method of the present invention, cover members 48 are attached to reject die sites 36 immediately after identification of the defective substrates 12 (i.e., immediately after Step 1). Alternatively, the cover members 48 of the support element 42 may be attached to reject die sites just prior to the matching of dice to the support element 42 functional die sites 50 (i.e., just prior to Step 2).

[0038] According to a second method of the present invention, dice are matched to functional dies sites, i.e., uncovered die sites (Step 2 in FIG. 4) and cover members 48 are then attached to the reject die sites 36.

[0039] According to a third method of the present invention, after the dice are matched with functional die sites (Step 2 in FIG. 4), adhesive is applied to all of the die sites (Step 3). Each die is attached to the matched die site on the support element via the adhesive. The adhesive typically comprises an epoxy, acrylic, silicone, or polyimide adhesive material, such as LOC tape, that will be sandwiched between the bottom of the die and the matched die site. Prior to die attachment, during die attachment or just following die attachment, the cover members 48 of the support element 42 are attached to the reject die sites 36. Depending upon the attachment process chosen, the process may require a follow-on cure in a cure oven. Likewise, the attachment process may include placing the dice and cover members 48 on an adhesive comprising an uncured epoxy that has been applied to the die sites. The dice and cover members may be held at a specific pressure by die attachment equipment having a surface contact tool or an edge contact only tool (collet). The dice (and, if necessary depending upon the cover member material, the cover members 48) are pressed down into the adhesive at a specific pressure by the tool and held in place long enough to ensure adhesion.

[0040] Adhesive may, alternatively, be applied to the dice and cover members 48 rather than the die sites (or to both the dice and to the die sites). If the cover members 48 comprise a material that does not carry its own adhesive (e.g., if the cover member is not self-adhesive tape) this method (in a single step) applies the required adhesive for the cover members 48 along with adhesive that must be applied to attach the dice. This method may be more efficient for those support elements 42 including cover members 48 that do not comprise self-adhesive materials. If the cover member 48 is self-adhesive, it would not be necessary to apply adhesive to the reject die sites or the cover members 48. Depending upon the materials used, self-adhesive cover members 48 may be used in conjunction with the adhesive used to attach dice. For example, during Step 3, adhesive such as LOC tape may be applied to all die sites (functional and reject sites) and the dice and self-adhesive cover members 48 may then be attached to the LOC tape on the functional and reject die sites, respectively.

[0041] According to a fourth method of the present invention, the cover members 48 of support element 42 are attached to reject die sites following a awire bonding process (Step 5 in FIG. 4). The wire bonding process connects the electrical circuitry of the functional substrates 12 to the electrical circuitry of the attached die. Specifically, bond pads of each of the dice are electrically connected to the corresponding die sites on the support element. The wire bond process may be performed using conventional wire bonding methods known to persons skilled in the art.

[0042] Fabrication of a semiconductor package 70 (FIG. 3A) utilizing the support element 42 of the present invention (FIGS. 2A and 2B) may then be completed. Specifically, following the wire bond process (Step 5), a polyimide protective layer may be applied to the face of the dice. Next, the support element 42 (including substrates 56 and attached dice 74 or cover members 48) is encapsulted using conventional means and materials as known to persons skilled in the art (Step 6 in FIG. 4). Typically, the dice 74, cover members 48 and substrates 56 of the support element 42 are encapsulated in a suitable plastic material, depending upon the intended use of the semiconductor package being fabricated.

[0043] A conventional solder ball attachment process may then be performed and the solder reflowed (Step 7). After the encapsulation and solder ball attach steps, a trim and form operation separates the packages (singulation) and shapes the leads into a desired configuration (Step 8 in FIG. 4). Individual semiconductor packages 70, 72 (as shown in FIGS. 3A and 3B) made utilizing the support element 42 of the present invention are then completed.

[0044] With reference to Step 4A in FIG. 4, in yet another method of the present invention, reject die sites 36 may be identified following or during the adhesive application process (Step 3). Dies are then attached to functional die sites and cover members 48 (e.g., reject dies) are attached to reject die sites 36 (Step 4B). The method would then proceed to Steps 5-8, as illustrated in FIG. 4 and discussed above.

[0045] Semiconductor packages 70 and 72 illustrated in FIGS. 3A and 3B were made using the support element 42 and methods of the present invention. Semiconductor package 70 illustrated in FIG. 3A is the package resulting from attachment of a functional die to a functional substrate 12 or functional die site 50 of the support element 42. Defective semiconductor package 72 illustrated in FIG. 3B is the package resulting from attachment of a cover member 48 to a reject die site of the support element 42.

[0046] Referring to FIGS. 3A and 3B, both the functional and the defective semiconductor packages 70, 72 include the substrate 56 having a planar die attach surface or die site 50 (defective package 72 includes reject die site 36, FIG. 3B). Both semiconductor packages 70, 72 include the features of the support element 42 discussed above. That is, both packages 70, 72 include an opposing conductor surface 76 wherein conductors 47 are formed in a required pattern. Wire bond slots 64 through the substrates 56 provide access for the bonding wires 80. The bonding wires 80 are connected to the conductors 47 and to conductor bond pads (not shown) on the die 74 (FIG. 3A). A glob top 82 is formed over the bonding wires 80 for protection. A solder mask 84 forms vias 86 to the conductors 47 and solder ball bonding pads 90. Solder balls 88 are attached to the conductors 47 through the vias 86.

[0047] The functional semiconductor package 70 further includes a die 74 attached to the die site 50 (FIG. 3A). The defective semiconductor package 72 merely includes cover member 48 (that may comprise, for example, a reject die) attached to the reject die site 36. (Thus, little is lost in production of the defective package but significant manufacturing costs are saved by utilizing support elements having functional and defective substrates without sacrificing functional dice or contaminating “adjacent dice,” as discussed above). The functional semiconductor package 70 further include adhesive layer 92. (The defective semiconductor package 72 may also includes an adhesive layer if the cover member 48 attached to the substrate 56 was not self-adhesive.) An encapsulating resin 92 encapsulates the die 74 and cover member 48, respectively (FIGS. 3A and 3B).

[0048] Whereas the invention has been described with reference to multiple embodiments of the support element 42 and representative methods, it will be understood that the invention is not limited to those embodiments. On the contrary, the invention is intended to encompass all modifications, alternatives, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims.