DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0098] The constitution of the present invention will be described with reference to FIG. 1 .

[0099] Herein, a display device with 2 ⁿ (n is a natural number of 2 or more) gray-scale will be described. The present invention is not limited to 2 ⁿ gray scale, and is applicable to a display device using another gray-scale.

[0100] Reference numeral 101 denotes a monitor EL element (second EL element), 102 denotes a buffer amplifier, and A ₁ to A _n denote constant current sources for allowing constant currents I ₁ to I _n to flow, respectively.

[0101] In the present specification, the constant current source is assumed to be an element for outputting a constant current from its output terminal at all times.

[0102] As the constant current source of the display device according to the present invention, those which have a known structure can be arbitrarily used.

[0103] An EL element (first EL element) of each pixel in a pixel portion and the monitor EL element (second EL element) 101 are respectively produced so as to have a first electrode, a second electrode, and an EL layer provided between the first electrode and the second electrode, and have substantially the same I-V characteristics of the EL layer at the same temperature.

[0104] Reference numeral 103 denotes a switch which selects either of the constant current sources A ₁ to A _n , thereby connecting the output terminal thereof to one electrode (first electrode) of the monitor EL element (second EL element) 101 .

[0105] The monitor EL element (second EL element) 101 is formed on the same substrate on which a pixel portion is formed. In the present specification, the substrate on which the pixel portion is formed is referred to as a “pixel substrate”.

[0106] The monitor EL element (second EL element) and the EL element (first EL element) in the pixel portion can be produced simultaneously.

[0107] The constant current sources A ₁ to A _n and the buffer amplifier 102 are collectively denoted by 1001 . The portion 1001 may be formed on the pixel substrate, formed on a single crystal IC chip so as to be attached to the pixel substrate, or produced on an external substrate.

[0108] It is assumed that one electrode (first electrode) of the monitor EL element (second EL element) 101 is connected to an output terminal of the constant current source A ₁ via the switch 103 . At this time, a constant current I ₁ is input between both electrodes (i.e., first electrode and second electrode) of the monitor EL element (second EL element) 101 .

[0109] When an environment temperature is changed, the current I ₁ flowing between both electrodes (first electrode and second electrode) of the monitor EL element (second EL element) 101 connected to the constant current source A ₁ is not changed; however, a voltage between both electrodes (first electrode and second electrode) of the monitor EL element (second EL element) 101 is changed due to temperature characteristics of the EL element shown in FIG. 4 .

[0110] The electrode (second electrode) of the monitor EL element (second EL element) 101 , that is not connected to the constant current source A ₁ , is supplied with a constant electric potential. This constant electric potential is set to be substantially the same as the electric potential of a counter electrode (second electrode) of the EL element (first EL element) in the pixel portion during a display period.

[0111] The buffer amplifier 102 has a non-inversion input terminal (+), an inversion input terminal (−), and an output terminal. The buffer amplifier 102 has a function of preventing the electric potential input to the non-inversion input terminal (+) from being changed by a load and wiring resistance connected to the output terminal.

[0112] As the buffer amplifier of the display device according to the present invention, those which have a known structure can be arbitrarily used.

[0113] The non-inversion input terminal (+) of the buffer amplifier 102 is connected to the electrode (first electrode) of the monitor EL element (second EL element), which is connected to the output terminal of the constant current source A ₁ , and is supplied with an electric potential of the electrode (first electrode) of the monitor EL element (second EL element). The electric potential of the electrode (first electrode) of the monitor EL element (second EL element) is input to a power supply line 104 via the buffer amplifier 102 . When an EL driving TFT of a pixel connected to the power supply line 104 is turned on, the electric potential of the electrode (first electrode) of the monitor EL element (second EL element) is input to the first electrode of the EL element (first EL element) in the pixel portion.

[0114] The electric potential of the electrode (first electrode) of the monitor EL element (second EL element), which is connected to the output terminal of the constant current source, is changed in accordance with a temperature so as to allow a set constant current of the connected constant current source to flow. This electric potential becomes an electric potential of the pixel electrode (first electrode) of the EL element (first EL element) of the pixel. Thus, during a display period, the same voltage as that applied between both electrodes (first electrode and second electrode) of the monitor EL element (second EL element) is applied between both electrodes (first electrode and second electrode) of the EL element (first EL element) of the pixel with a light-emitting state selected. Accordingly, a constant current flows between both electrodes (first electrode and second electrode) of the EL element (first EL element) of the pixel.

[0115] As described above, a voltage, that is changed so as to allow a constant current to flow, is applied between the first electrode and the second electrode of the EL element (first EL element) in the pixel portion even when a temperature is changed. Thus, a current flowing through the EL element (first EL element) in the pixel portion can be kept constant to be irrespective of the change in temperature.

[0116] Since the EL element in the pixel portion and the monitor EL element are formed on the same substrate, substantially the same I-V characteristics are obtained at the same temperature. Therefore, the EL element (first EL element) in the pixel portion can be lightened with required lightness by adjusting a current flowing between the first electrode and the second electrode of the monitor EL element (second EL element).

[0117] Furthermore, the remaining constant current sources A ₂ to A _n are successively selected by switching the switch 103 , and constant currents I ₂ to I _n are supplied to the monitor EL element (second EL element). Voltages generated between the first electrode and the second electrode of the monitor EL element (second EL element) by the constant currents I ₂ to I _n are applied between the first electrode and the second electrode of the EL element (first EL element) in the pixel portion by using the buffer amplifier 102 .

[0118] Hereinafter, a driving method of the present invention will be described with reference to a timing chart in FIG. 2 . In FIG. 2 , the same reference numerals as those in FIG. 1 are partially used.

[0119] One frame period is divided into a plurality of sub-frame periods SF ₁ to SF _n . For each sub-frame period SF ₁ to SF _n , one of the constant current sources A ₁ to A _n shown in FIG. 1 is successively selected by the switch 103 , and the output terminal of the selected constant current source and the first electrode of the monitor EL element (second EL element) are connected to each other. At this time, voltages V ₁ to V _n corresponding to the constant currents I ₁ to I _n are applied to the power supply line.

[0120] The sub-frame periods include write periods Ta ₁ to Ta _n for supplying signals to all the pixels and selecting whether or not each pixel emits light, and display periods Ts ₁ to Ts _n in which EL elements (first EL elements) of all the pixels emit light or not in accordance with the signals supplied during the write periods Ta ₁ to Ta _n .

[0121] It is assumed that the lengths of the write periods Ta ₁ to Ta _n are the same, and the lengths of the display periods Ts ₁ to Ts _n are also the same.

[0122] For each sub-frame period, the constant current sources A ₁ to A _n are successively selected, and the electric potential of the first electrode of the monitor EL element (second EL element) is changed in accordance with the constant currents I ₁ to I _n output from the respective constant current sources A ₁ to A _n , and the electric potential of the power supply line is changed to V ₁ to V _n in accordance with the electric potential.

[0123] During the respective write periods Ta ₁ to Ta _n , the electric potential of a counter electrode (second electrode) of the EL element (first EL element) in the pixel portion is kept at the same as the respective electric potentials V ₁ to V _n of the power supply line. Therefore, during the write periods Ta ₁ to Ta _n , the EL driving voltage is 0 volt. On the other hand, during the display periods Ts ₁ to Ts _n , the electric potential of the counter electrode (second electrode) of the EL element (first EL element) in the pixel portion is set so as to cause a potential difference with respect to the electric potential of the power supply line to such a degree that the EL element emits light.

[0124] The electric potential of the counter electrode (second electrode) of the EL element (first EL element) in the pixel portion during the write period is changed, corresponding to the electric potential of the power supply line varied every sub-frame period. The electric potential of the counter electrode during the display period may be the same during all the sub-frame periods.

[0125] Herein, it is assumed that the electric potential of the counter electrode of the EL element (first EL element) in the pixel portion during the display periods Ts ₁ to Ts _n is 0 volt. Then, the EL driving voltage applied between both electrodes (first electrode and second electrode) of the EL element (first EL element) of the pixel with a light-emitting state selected during the display periods Ts ₁ to Ts _n is changed to V ₁ to V _n every sub-frame period.

[0126] Due to the EL driving voltages V ₁ to V _n , constant currents I _EL1 to I _Eln that are proportional to the constant currents I ₁ to I _n output from the constant current sources A ₁ to A _n flow through the EL element (first EL element) in the pixel portion. The EL element has the property that its light-emitting brightness is substantially proportional to the currents I _EL1 to I _Eln flowing through the element. Therefore, if the ratio of the currents I ₁ to I _n (i.e., the currents I ₁ to I _n flowing through the constant current sources A ₁ to A _n ), I ₁ :I ₂ : . . . :I _n−1 :I _n , is set to be 2 ⁰ :2 ⁻¹ : . . . :2 ⁻⁽ⁿ⁻²⁾ : 2 ⁻⁽ⁿ⁻¹⁾ , the ratio of light-emitting brightness Lm ₁ to Lm _n in the case where the EL element (first EL element) in the pixel portion is allowed to emit light during each of the display periods, Ts ₁ to Ts _n , Lm ₁ :Lm ₂ : . . . :Lm _(n−1) :Lm _n , also becomes 2 ⁰ :2 ⁻¹ : . . . :2 ⁻⁽ⁿ⁻²⁾ :2 ⁻⁽ⁿ⁻¹⁾ .

[0127] At this time, by adding up the light emission amount during the display periods in which the pixel is lightened during one frame period, the brightness of the pixel is determined. For example, at n=8, it is assumed that the brightness in the case where the pixel is lightened during all the display periods Ts ₁ to Ts _n is 100%. When the pixel emits light during Ts ₁ and Ts ₂ , about 75% brightness can be exhibited. On the other hand, when the display periods Ts ₃ , Ts ₅ and Ts ₈ are selected, about 16% brightness can be exhibited.

[0128] The display periods Ts ₁ to Ts _n may appear in any order. For example, it is also possible to allow the display periods to appear in the order of Ts ₁ , Ts ₄ , Ts ₃ , Ts ₂ , . . . , in one frame period.

[0129] Furthermore, in the case where a plurality of constant current sources for respectively outputting currents with different values are present as described above, it is also possible to exhibit gray-scale by selecting the same constant current source during a plurality of sub-frame periods in one frame period, and varying the length of the display periods of the respective sub-frame periods for which the same constant current source is selected.

[0130] For example, as shown in a timing chart in FIG. 19 , it is also possible to exhibit gray-scale by selecting the same constant current source during a plurality of sub-frame periods of n sub-frame periods in one frame period, and varying the length of the display periods of the respective sub-frame periods for which the same constant current source is selected.

[0131] In FIG. 19 , the same constant current source A ₁ is selected for the sub-frame periods SF ₁ and SF ₂ . At this time, the lengths of display periods Ts ₁ and Ts ₂ of the sub-frame periods SF ₁ and SF ₂ are different.

[0132] As described above, by combining a procedure of varying the length of display periods of different sub-frame periods and a procedure of varying a current flowing between both electrodes (first electrode and second electrode) of the monitor EL element (second EL element) for different sub-frame periods, the display period of lower order bits is set to be long, and the number of constant current sources required for a gray-scale display can be decreased.

[0133] Furthermore, in the case where the values of currents output from n (n is a natural number of 2 or more) constant current sources are the same, during one frame period, output terminals of m (m is a natural number of n or less) constant current sources are connected to the first electrode of the monitor EL element (second EL element) during a certain sub-frame period, and output terminals of k (k is a natural number of n or less, different from m) constant current sources are connected to the first electrode of the monitor EL element (second EL element) during another sub-frame period.

[0134] Thus, the sum of the output currents from the plurality of selected constant current sources may be set as a current flowing between the first electrode and the second electrode of the monitor EL element (second EL element).

[0135] Embodiments

[0136] Hereinafter, embodiments of the present invention will be described.

[0137] Embodiment 1

[0138] In the present embodiment, a configuration of a buffer amplifier of the display device according to the present invention will be described.

[0139] FIG. 3 shows an exemplary buffer amplifier produced by using TFTs.

[0140] The buffer amplifier is composed of TFTs 1901 to 1909 , a capacitor 1910 , constant current sources 1911 and 1912 , and the like. The TFTs 1901 , 1902 , 1906 , and 1909 are n-channel type TFTs. The TFTs 1903 to 1905 , 1907 , and 1908 are p-channel type TFTs.

[0141] Reference numeral 1930 denotes a higher-potential side power source line, and 1931 denotes a lower-potential side power source line.

[0142] Hereinafter, an operation of the buffer amplifier will be described in detail.

[0143] A differential amplifier 1921 composed of the TFTs 1901 and 1902 will be described. Because of the difference in voltage input to a gate electrode of the TFT 1901 corresponding to a non-inversion input terminal of the buffer amplifier and a gate electrode of the TFT 1902 corresponding to an inversion input terminal of the buffer amplifier, the amount of a current flowing between a drain and a source of each TFT is varied. These currents are denoted with i 1 and i 2 .

[0144] A current mirror circuit 1922 is composed of the TFTs 1903 and 1904 . Since a gate electrode of the TFT 1903 is connected to a gate electrode of the TFT 1904 , the electric potentials of the gate electrodes of these two TFTs are equal. Therefore, the amount of a current flowing between the source and the drain of the TFT 1903 becomes equal to that of the TFT 1904 . Accordingly, a current i 3 corresponding to the difference between the currents i 1 and i 2 flowing through the TFTs 1901 and 1902 of the differential amplifier 1921 must be input to the differential amplifier 1921 .

[0145] The current i 3 is supplied from the capacitor 1910 . Because of this, a potential difference V between the electrodes of the capacitor 1910 is increased. The potential difference V is input to a source ground amplifier 1923 .

[0146] The source ground amplifier 1923 is composed of the TFT 1905 . The potential difference V input to the source ground amplifier 1923 becomes a potential difference between a source and a drain of the TFT 1905 . A current i 4 flows corresponding to the potential difference V. Herein, the constant current source 1912 allows only a constant current i 0 to flow. Therefore, a difference i 5 between the currents i 4 and i 0 is input to a source follow buffer circuit 1924 . The current i 5 is increased corresponding to the amplified potential difference V.

[0147] The source follow buffer circuit 1924 is composed of the TFTs 1906 and 1907 . An input i 5 from the source ground amplifier 1923 is input to a gate electrode of the TFT 1906 . Due to the input current i 5 , the amount of a current i 6 flowing between a source and a drain of the TFT 1906 is increased. More specifically, a large current is output from the buffer amplifier.

[0148] As described above, the buffer amplifier amplifies and outputs a current.

[0149] In the present embodiment, although the differential circuit is composed of an n-channel type TFT, it may be composed of a p-channel type TFT.

[0150] Embodiment 2

[0151] In Embodiment 2, a method of simultaneously manufacturing TFTs of a pixel portion of display device of the present invention and driving circuit portions provided in the periphery thereof (a source signal line driving circuit and a gate signal line driving circuit). However, in order to simplify the explanation, a CMOS circuit, which is the basic circuit for the driving circuit, is shown in the figures.

[0152] First, as shown in FIG. 9A, a base film 5002 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film is formed on a substrate 5001 made of glass such as barium borosilicate glass or alumino borosilicate glass, typified by #7059 glass or #1737 glass of Corning Inc. For example, a silicon nitride oxide film 5002 a fabricated from SiH ₄ , NH ₃ and N ₂ O by a plasma CVD method is formed with a thickness of 10 to 200 nm (preferably 50 to 100 nm), and a hydrogenated silicon nitride oxide film 5002 b similarly fabricated from SiH ₄ and N ₂ O is formed with a thickness of 50 to 200 nm (preferably 100 to 150 nm) to form a lamination. In Embodiment 2, although the base film 5002 is shown as the two-layer structure, the film may be formed of a single layer film of the foregoing insulating film or as a lamination structure of more than two layers.

[0153] Island-like semiconductor films 5003 to 5006 are formed of a crystalline semiconductor film manufactured by using a laser crystallization method on a semiconductor film having an amorphous structure, or by using a known thermal crystallization method. The thickness of the island-like semiconductor films 5003 to 5006 is set from 25 to 80 nm (preferably between 30 and 60 nm). There is no limitation on the crystalline semiconductor film material, but it is preferable to form the film from a silicon or a silicon germanium (SiGe) alloy.

[0154] A laser such as a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser is used for manufacturing the crystalline semiconductor film in the laser crystallization method. A method of condensing laser light emitted from a laser oscillator into a linear shape by an optical system and then irradiating the light to the semiconductor film may be employed when these types of lasers are used. The crystallization conditions may be suitably selected by the operator, but the pulse oscillation frequency is set to 30 Hz, and the laser energy density is set from 100 to 400 mJ/cm ² (typically between 200 and 300 mJ/cm ² ) when using the excimer laser. Further, the second harmonic is utilized when using the YAG laser, the pulse oscillation frequency is set from 1 to 10 kHz, and the laser energy density may be set from 300 to 600 mJ/cm ² (typically between 350 and 500 mJ/cm ² ). The laser light which has been condensed into a linear shape with a width of 100 to 1000 μm, for example 400 μm, is then irradiated over the entire surface of the substrate. This is performed with an overlap ratio of 80 to 98% in case of the excimer laser.

[0155] Next, a gate insulating film 5007 is formed covering the island-like semiconductor films 5003 to 5006 . The gate insulating film 5007 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by a plasma CVD method or a sputtering method. A 120 nm thick silicon nitride oxide film is formed in Embodiment 2. The gate insulating film 5007 is not limited to such a silicon nitride oxide film, of course, and other insulating films containing silicon may also be used, in a single layer or in a lamination structure. For example, when using a silicon oxide film, it can be formed by the plasma CVD method with a mixture of TEOS (tetraethyl orthosilicate) and O ₂ , at a reaction pressure of 40 Pa, with the substrate temperature set from 300 to 400° C., and by discharging at a high frequency (13.56 MHZ) with electric power density of 0.5 to 0.8 W/cm ² . Good characteristics of the silicon oxide film thus manufactured as a gate insulating film can be obtained by subsequently performing thermal annealing at 400 to 500° C.

[0156] A first conductive film 5008 and a second conductive film 5009 are then formed on the gate insulating film 5007 in order to form gate electrodes. In Embodiment 2, the first conductive film 5008 is formed from Ta with a thickness of 50 to 100 nm, and the second conductive film 5009 is formed from W with a thickness of 100 to 300 nm.

[0157] The Ta film is formed by sputtering, and sputtering of a Ta target is performed by using Ar. If an appropriate amount of Xe or Kr is added to the Ar during sputtering, the internal stress of the Ta film will be relaxed, and film peeling can be prevented. The resistivity of an α phase Ta film is on the order of 20 μΩcm, and the Ta film can be used for the gate electrode, but the resistivity of a β phase Ta film is on the order of 180 μΩcm and the Ta film is unsuitable for the gate electrode. The phase Ta film can easily be obtained if a tantalum nitride film, which possesses a crystal structure near that of α phase Ta, is formed with a thickness of 10 to 50 nm as a base for Ta in order to form the β phase Ta film.

[0158] The W film is formed by sputtering with W as a target. The W film can also be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). Whichever is used, it is necessary to make the film low resistant in order to use it as the gate electrode, and it is preferable that the resistivity of the W film be set 20 μΩcm or less. The resistivity can be lowered by enlarging the crystals of the W film, but for cases where there are many impurity elements such as oxygen within the W film, crystallization is inhibited, and the film becomes high resistant. A W target having a purity of 99.9999% is thus used in sputtering. In addition, by forming the W film while taking sufficient care such that no impurities from the inside of the gas phase are introduced at the time of film formation, a resistivity of 9 to 20 μΩcm can be achieved.

[0159] Note that although the first conductive film 5008 and the second conductive film 5009 are formed from Ta and W. respectively, in Embodiment 2, the conductive films are not limited to these. Both the first conductive film 5008 and the second conductive film 5009 may also be formed from an element selected from the group consisting of Ta, W, Ti, Mo, Al, and Cu, or from an alloy material or a chemical compound material having one of these elements as its main constituent. Further, a semiconductor film, typically a polysilicon film, into which an impurity element such as phosphorous is doped, may also be used. Examples of preferable combinations other than that in Embodiment 2 include: the first conductive film formed from tantalum nitride (TaN) and the second conductive film formed from W; the first conductive film formed from tantalum nitride (TaN) and the second conductive film formed from Al; and the first conductive film formed from tantalum nitride (TaN) and the second conductive film formed from Cu.

[0160] Next, a mask 5010 is formed from resist, and a first etching process is performed in order to form electrodes and wirings. An ICP (inductively coupled plasma) etching method is used in Embodiment 2. A gas mixture of CF ₄ and Cl ₂ is used as an etching gas, and a plasma is generated by applying a 500 W RF electric power (13.56 MHZ) to a coil shape electrode at 1 Pa. A 100 W RF electric power (13.56 MHZ) is also applied to the substrate side (test piece stage), effectively applying a negative self-bias voltage. The W film and the Ta film are both etched on the same order when CF ₄ and Cl ₂ are mixed.

[0161] Edge portions of the first conductive layer and the second conductive layer are made into a tapered shape in accordance with the effect of the bias voltage applied to the substrate side with the above etching conditions by using a suitable resist mask shape. The angle of the tapered portions is from 15° to 45°. The etching time may be increased by approximately 10 to 20% in order to perform etching without any residue on the gate insulating film. The selectivity of a silicon nitride oxide film with respect to a W film is from 2 to 4 (typically 3), and therefore approximately 20 to 50 nm of the exposed surface of the silicon nitride oxide film is etched by this over-etching process. First shape conductive layers 5011 to 5016 (first conductive layers 5011 a to 5016 a and second conductive layers 5011 b to 5016 b ) are thus formed of the first conductive layer and the second conductive layer by the first etching process. At this point, regions of the gate insulating film 5007 not covered by the first shape conductive layers 5011 to 5016 are made thinner by approximately 20 to 50 nm by etching. ( FIG. 9B )

[0162] Then, a first doping process is performed to add an impurity element for imparting a n-type conductivity. ( FIG. 9B ) Doping may be carried out by an ion doping method or an ion injecting method. The condition of the ion doping method is that a dosage is 1×10 ¹³ to 5×10 ¹⁴ atoms/cm ² , and an acceleration voltage is 60 to 100 keV. As the impurity element for imparting the n-type conductivity, an element belonging to group 15, typically phosphorus (P) or arsenic (As) is used, but phosphorus is used here. In this case, the conductive layers 5011 to 5015 become masks to the impurity element to impart the n-type conductivity, and first impurity regions 5017 to 5025 are formed in a self-aligning manner. The impurity element to impart the n-type conductivity in the concentration range of 1×10 ²⁰ to 1×10 ²¹ atoms/cm ³ is added to the first impurity regions 5017 to 5025 .

[0163] Next, as shown in FIG. 9C, a second etching process is performed without removing the mask formed from resist. The etching gas of the mixture of CF ₄ , Cl ₂ and O ₂ is used, and the W film is selectively etched. At this point, second shape conductive layers 5026 to 5031 (first conductive layers 5026 a to 5031 a and second conductive layers 5026 b to 5031 b ) are formed by the second etching process. Regions of the gate insulating film 5007 , which are not covered with the second shape conductive layers 5026 to 5031 are made thinner by about 20 to 50 nm by etching.

[0164] An etching reaction of the W film or the Ta film by the mixture gas of CF ₄ and Cl ₂ can be guessed from a generated radical or ion species and the vapor pressure of a reaction product. When the vapor pressures of fluoride and chloride of W and Ta are compared with each other, the vapor pressure of WF ₆ of fluoride of W is extremely high, and other WCl ₅ , TaF ₅ , and TaCl ₅ have almost equal vapor pressures. Thus, in the mixture gas of CF ₄ and Cl ₂ , both the W film and the Ta film are etched. However, when a suitable amount of O ₂ is added to this mixture gas, CF ₄ and O ₂ react with each other to form CO and F, and a large number of F radicals or F ions are generated. As a result, an etching rate of the W film having the high vapor pressure of fluoride is increased. On the other hand, with respect to Ta, even if F is increased, an increase of the etching rate is relatively small. Besides, since Ta is easily oxidized as compared with W, the surface of Ta is oxidized by addition of O ₂ . Since the oxide of Ta does not react with fluorine or chlorine, the etching rate of the Ta film is further decreased. Accordingly, it becomes possible to make a difference between the etching rates of the W film and the Ta film, and it becomes possible to make the etching rate of the W film higher than that of the Ta film.

[0165] Then, as shown in FIG. 10A, a second doping process is performed. In this case, a dosage is made lower than that of the first doping process and under the condition of a high acceleration voltage, an impurity element for imparting the n-type conductivity is doped. For example, the process is carried out with an acceleration voltage set to 70 to 120 keV and at a dosage of 1×10 ¹³ atoms/cm ² , so that new impurity regions are formed inside of the first impurity regions formed into the island-like semiconductor layers in FIG. 9B . Doping is carried out such that the second shape conductive layers 5026 to 5030 are used as masks to the impurity element and the impurity element is added also to the regions under the first conductive layers 5026 a to 5030 a . In this way, third impurity regions 5032 to 5036 are formed. The concentration of phosphorous (P) added to the third impurity regions has a gentle concentration gradient in accordance with the thickness of tapered portions of the first conductive layers 5026 a to 5030 a . Note that in the semiconductor layer that overlap with the tapered portions of the first conductive layers 5026 a to 5030 a , the concentration of impurity element slightly falls from the end portions of the tapered portions of the first conductive layers 5026 a to 5030 a toward the inner portions, but the concentration keeps almost the same level.

[0166] As shown in FIG. 10B, a third etching process is performed. This is performed by using a reactive ion etching method (RIE method) with an etching gas of CHF ₃ . The tapered portions of the first conductive layers 5026 a to 5031 a are partially etched, and the region in which the first conductive layers overlap with the semiconductor layer is reduced by the third etching process. Third shape conductive layers 5037 to 5042 (first conductive layers 5037 a to 5042 a and second conductive layers 5037 b to 5042 b ) are formed. At this point, regions of the gate insulating film 5007 , which are not covered with the third shape conductive layers 5037 to 5042 are made thinner by about 20 to 50 nm by etching.

[0167] By the third etching process, in the third impurity regions 5032 to 5036 before performed the third etching process, third impurity regions 5032 a to 5036 a , which overlap with the first conductive layers 5037 a to 5042 a , and second impurity regions 5032 b to 5236 b between the first impurity regions and the third impurity regions are formed.

[0168] Then, as shown in FIG. 10 C, fourth impurity regions 5043 to 5054 having a conductivity type opposite to the first conductivity type are formed in the island-like semiconductor layers 5004 and 5006 forming p-channel TFTs. The third conductive layers 5038 b and 5041 b are used as masks to an impurity element, and the impurity regions are formed in a self-aligning manner. At this time, the whole surfaces of the island-like semiconductor layers 5003 , 5005 and the wiring portion 5042 , which form n-channel TFTs are covered with a resist mask 5200 . Phosphorus is added to the impurity regions 5043 to 5054 at different concentrations, respectively. The regions are formed by an ion doping method using diborane (B ₂ H ₆ ) and the impurity concentration is made 2×10 ²⁰ to 2×10 ²¹ atoms/cm ³ in any of the regions.

[0169] By the steps up to this, the impurity regions are formed in the respective island-like semiconductor layers. The third shape conductive layers 5037 to 5041 overlapping with the island-like semiconductor layers function as gate electrodes. The conductive layer 5042 functions as an island-like source signal line.

[0170] After the resist mask 5200 is removed, a step of activating the impurity elements added in the respective island-like semiconductor layers for the purpose of controlling the conductivity type. This step is carried out by a thermal annealing method using a furnace annealing oven. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. The thermal annealing method is performed in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less and at 400 to 700° C., typically 500 to 600° C. In Embodiment 2, a heat treatment is conducted at 500° C. for 4 hours. However, in the case where a wiring material used for the third conductive layers 5037 to 5042 is weak to heat, it is preferable that the activation is performed after an interlayer insulating film (containing silicon as its main ingredient) is formed to protect the wiring line or the like.

[0171] Further, a heat treatment at 300 to 450° C. for 1 to 12 hours is conducted in an atmosphere containing hydrogen of 3 to 100%, and a step of hydrogenating the island-like semiconductor layers is conducted. This step is a step of terminating dangling bonds in the semiconductor layer by thermally excited hydrogen. As another means for hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be carried out.

[0172] Next, as shown in FIG. 11A, a first interlayer insulating film 5055 having a thickness of 100 to 200 nm is formed of a silicon nitride oxide film. A second interlayer insulating film 5056 made of an organic insulator material is formed thereon. Contact holes are then formed with respect to the first interlayer insulating film 5055 , the second interlayer insulating film 5056 , and the gate insulating film 5007 , respective wirings (including connection wirings and signal lines) 5057 to 5062 , and 5064 are formed by patterning, and then, a pixel electrode 5063 that contacts with the connection wiring 5062 is formed by patterning.

[0173] Next, the film made from organic resin is used for the second interlayer insulating film 5056 . As the organic resin, polyimide, polyamide, acryl, BCB (benzocyclobutene) or the like can be used. Especially, since the second interlayer insulating film 5056 has rather the meaning of flattening, acryl excellent in flatness is desirable. In Embodiment 2, an acryl film is formed to such a thickness that stepped portions formed by the TFTs can be adequately flattened. The thickness is preferably made 1 to 5 μm (more preferably 2 to 4 μm).

[0174] In the formation of the contact holes, dry etching or wet etching is used, and contact holes reaching the n-type impurity regions 5017 , 5018 , 5021 and 5023 or the p-type impurity regions 5043 to 5054 , a contact hole reaching the wiring 5042 , a contact hole reaching the power source supply line (not shown), and contact holes reaching the gate electrodes (not shown) are formed, respectively.

[0175] Further, a lamination film of a three layer structure, in which a 100 nm thick Ti film, a 300 nm thick aluminum film containing Ti, and a 150 nm thick Ti film are formed in succession by sputtering, is patterned into a desirable shape, and the resultant lamination film is used as the wirings (including connection wirings) 5057 to 5062 , and 5064 . Of course, other conductive films may be used.

[0176] Furthermore, in Embodiment 2, an ITO film is formed with a thickness of 110 nm, and patterning is performed to form the pixel electrode 5063 . The pixel electrode 5063 is arranged so as to contact and overlap the connection wiring 5062 so that contact is obtained. Further, a transparent conductive film in which zinc oxide (ZnO) of 2 to 20% is mixed with indium oxide may be used. This pixel electrode 5063 corresponds to an anode of an EL element. ( FIG. 11A )

[0177] Next, as shown in FIG. 11 B, an insulating film containing silicon (a silicon oxide film in Embodiment 2) is formed with a thickness of 500 nm, an opening portion is formed at the position corresponding to the pixel electrode 5063 , and then, a third interlayer insulating film 5065 that functions as a bank is formed. In forming the opening portion, side walls having a tapered shape may be easily formed by using wet etching. The deterioration of the EL layer due to stepped portion becomes a remarkable problem if the side walls of the opening portion are sufficiently flat.

[0178] An EL layer 5066 and a cathode (MgAg electrode) 5067 are formed next in succession, without exposure to the atmosphere, using a vacuum evaporation method. Note that the film thickness of the EL layer 5066 may be set from 80 to 200 nm (typically between 100 and 120 nm), and the thickness of the cathode 5067 may be set from 180 to 300 nm (typically 200 to 250 nm).

[0179] The EL layer and the cathode are formed one after another with respect to pixels corresponding to the color red, pixels corresponding to the color green, and pixels corresponding to the color blue. However, the EL layer is weak with respect to a solution, and therefore the EL layer and the cathode must be formed with respect to each of the colors without using a photolithography technique. It is preferable to cover areas outside of the desired pixels using a metal mask, and selectively form the EL layer and the cathode only in the necessary locations.

[0180] In other words, a mask is first set so as to cover all pixels except for those corresponding to the color red, and the EL layer for emitting red color light is selectively formed using the mask. Next, a mask is set so as to cover all pixels except for those corresponding to the color green, and the EL layer for emitting green color light is selectively formed using the mask. Similarly, a mask is set so as to cover all pixels except for those corresponding to the color blue, and the EL layer for emitting blue color light is selectively formed using the mask. Note that the use of all different masks is stated here, but the same mask may also be reused.

[0181] The method of forming three kinds of EL elements corresponding to the colors RGB is used here, but a method of combining a white color light emitting EL element and a color filter, a method of combining a blue or blue-green color light emitting EL element and a fluorescing body (fluorescing color conversion layer: CCM), a method of using a transparent electrode as a cathode (opposing electrode) and overlapping it with EL elements each corresponding to one of the colors RGB and the like may be used.

[0182] A known material can be used as the EL layer 5066 . Considering the driving voltage, it is preferable to use an organic material as the known material. For example, a four layer structure constituted of a hole injecting layer, a hole transporting layer, a light emitting layer and an electron injecting layer may be adopted as an EL layer.

[0183] Next, the cathode 5067 is formed using a metal mask on the pixels having the switching TFTs of which the gate electrodes are connected to the same gate signal line (pixels on the same line). Note that, in Embodiment 2, although MgAg is used as the cathode 5067 , the present invention is not limited to this. Other known materials may be used for the cathode 5067 .

[0184] Finally, a passivation film 5068 made of a silicon nitride film is formed with a thickness of 300 nm. The formation of the passivation film 5068 enables the EL layer 5066 to be protected against moisture and the like, and the reliability of the EL element can further be enhanced.

[0185] According to above-mentioned steps, the monitor EL element for (second EL element) can be formed simultaneously with the EL element (first EL element) of the pixel on the same substrate.

[0186] Consequently, the EL display device with the structure as shown in FIG. 11B is completed. Note that, in the manufacturing process of the EL display device in Embodiment 2, the source signal lines are formed from Ta and W, which are materials for forming gate electrodes, and the gate signal lines are formed from Al, which is a material for forming wirings, but different materials may be used.

[0187] Incidentally, the EL display device in Embodiment 2 exhibits the very high reliability and has the improved operational characteristic by providing TFTs having the most suitable structure in not only the pixel portion but also the driving circuit portion. Further, it is also possible to add a metallic catalyst such as Ni in the crystallization process, thereby increasing crystallinity. It therefore becomes possible to set the driving frequency of the source signal line driving circuit to 10 MHZ or higher.

[0188] First, a TFT having a structure in which hot carrier injection is reduced without decreasing the operating speed as much as possible is used as an n-channel TFT of a CMOS circuit forming the driving circuit portion. Note that the driving circuit referred to here includes circuits such as a shift register, a buffer, a level shifter, a latch in line-sequential drive, and a transmission gate in dot-sequential drive.

[0189] In Embodiment 2, the active layer of the n-channel TFT contains the source region, the drain region, the LDD region overlapping with the gate electrode with the gate insulating film sandwiched therebetween (Lov region), the offset LDD region not overlapping with the gate electrode with the gate insulating film sandwiched therebetween (Loff region), and the channel forming region.

[0190] Further, there is not much need to worry about degradation due to the hot carrier injection with the p-channel TFT of the CMOS circuit, and therefore LDD regions may not be formed in particular. It is of course possible to form LDD regions similar to those of the n-channel TFT, as a measure against hot carriers.

[0191] In addition, when using a CMOS circuit in which electric current flows in both directions in the channel forming region, namely a CMOS circuit in which the roles of the source region and the drain region interchange, it is preferable that LDD regions be formed on both sides of the channel forming region of the n-channel TFT forming the CMOS circuit, sandwiching the channel forming region. A circuit such as a transmission gate used in dot-sequential drive can be given as an example of such. Further, when a CMOS circuit in which it is necessary to suppress the value of the off current as much as possible is used, the n-channel TFT forming the CMOS circuit preferably has an Lov region. A circuit such as the transmission gate used in dot-sequential drive can be given as an example of such.

[0192] Note that, in practice, it is preferable to perform packaging (sealing), without exposure to the atmosphere, using a protecting film (such as a laminated film or an ultraviolet cured resin film) having good airtight properties and little outgassing, or a transparent sealing material, after completing through the state of FIG. 11B . At this time, the reliability of the EL element is increased by making an inert atmosphere on the inside of the sealing material and by arranging a drying agent (barium oxide, for example) inside the sealing material.

[0193] Further, after the airtight properties have been increased by the packaging process, a connector (flexible printed circuit: FPC) is attached in order to connect terminals led from the elements or circuits formed on the substrate with external signal terminals. Then, a finished product is completed. This state at which the product is ready for shipment is referred to as a display device throughout this specification.

[0194] Furthermore, in accordance with the process shown in Embodiment 2, the number of photo masks required for manufacture of a display device can be suppressed. As a result, the process can be shortened, and the reduction of the manufacturing cost and the improvement of the yield can be attained.

[0195] Embodiment 3

[0196] In this embodiment, an example in which an EL display device of the present invention is fabricated will be described.

[0197] FIG. 12A is a top view of an active EL display device using the present invention. In FIG. 12 A, reference numeral 4010 designates a substrate; 4011 , a pixel portion; 4012 , a source signal line driving circuit; and 4013 , a gate signal line driving circuit, and the pixel portion and the respective driving circuits lead to an FPC 4017 through wirings 4014 to 4016 and are connected to an external equipment.

[0198] At this time, a cover member 6000 , a seal member (also called a housing member) 7000 , and a sealant (second seal member) 7001 are provided so as to surround at least the pixel portion, preferably the driving circuits and the pixel portion.

[0199] FIG. 12B is a view showing a sectional structure of the EL display device of this embodiment. A driving circuit TFT (here, a CMOS circuit of a combination of an n-channel TFT and a p-channel TFT is shown) 4022 and a pixel portion TFT 4023 are formed on the substrate 4010 and a base film 4021 . These TFTs may be formed by using a well-known structure (top gate structure or bottom gate structure).

[0200] When the driving circuit TFT 4022 and the pixel portion TFT 4023 are completed, a pixel electrode 4027 electrically connected to a drain of the pixel portion TFT 4023 and made of a transparent conductive film is formed on an interlayer insulating film (leveling film) 4026 made of resin material. As the transparent conductive film, a compound (called ITO) of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used. After the pixel electrode 4027 is formed, an insulating film 4028 is formed, and an opening portion is formed on the pixel electrode 4027 .

[0201] Next, an EL layer 4029 is formed. As the EL layer 4029 , a laminate structure or a single layer structure may be adopted by freely combining well-known EL materials (hole injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer). A well-known technique may be used to determine the structure. The EL material includes a low molecular material and a high molecular (polymer) material. In the case where the low molecular material is used, a