Title:

Semiconductor memory and nonvolatile semiconductor memory having redundant circuitry for replacing defective memory cell

Document Type and Number:

United States Patent 20020012282

Kind Code:

Abstract:

Redundant cell arrays 201 of a plurality of columns are provided for replacing a defective bit line of a memory cell array 101. Each of the redundant cell arrays 201 is provided with a redundant sense amplifier circuit 105 separately from a sense amplifier circuit 103 of the memory cell array 101. A defective address storing circuit 108 stores a defective address of the memory cell array 101, an input/output terminal, to and from which data corresponding to the defective address are to be inputted and outputted, and a column set number of the redundant cell array which is to be replaced in accordance with the input/output terminal. An address comparator circuit 109 detects the coincidence of an input address with the defective address. A switch circuit 112 is controlled by the coincidence detection output to switch one corresponding to the defective address of a sense amplifier circuit to one selected by the set number in the redundant sense amplifier circuit, to connect it to a data input/output buffer 113. Thus, it is possible to provide a semiconductor memory capable of effectively relieving a plurality of defective columns and a defect in a boundary region in column directions of the cell array.

Inventors:

Saito, Hidetoshi (Yokohama-Shi, JP)
Kuriyama, Masao (Fujisawa-Shi, JP)
Honda, Yasuhiko (Yokohama-Shi, JP)
Kato, Hideo (Kawasaki-Shi, JP)

Plaque It!

What is claimed is:

1. A semiconductor memory comprising: a memory cell array having electrically rewritable memory cells; a plurality of redundant column cell arrays for relieving a defective memory cell in said memory cell array; a decoding circuit for selecting a memory cell of said memory cell array; a plurality of sense amplifier circuits for detecting read data of said memory cell array and for latching write data; data input/output buffers provided between each of said sense amplifier circuits and a corresponding one of data input/output terminals; a defective address storing circuit for storing a defective address of said memory cell array, an input/output terminal to and from which data corresponding to said defective address are inputted and outputted, and a set number for identifying one of said plurality of redundant column cell arrays, which is to be substituted so as to correspond to said input/output terminal; a plurality of redundant sense amplifier circuits for detecting read data of said plurality of redundant column cell arrays and for latching write data; an address comparator circuit for outputting a coincidence detection signal when an input address is coincident with said defective address held in said defective address storing circuit; and a switching circuit which is controlled by said coincidence detection signal for selectively connecting one of said sense amplifier corresponding to said defective address in said plurality of sense amplifier circuits or one of said redundant sense amplifier circuits identified by said set number in said plurality of redundant sense amplifier circuit, to said data input/output buffer.

2. A semiconductor memory as set forth in claim 1, herein said switching circuit comprises a sense amplifier switching circuit, and a plurality of data switching circuits provided so as to correspond to said plurality of sense amplifier circuits; said sense amplifier switching circuit selectively connects one of said plurality of redundant sense amplifier circuits to said plurality of data switching circuits; and said plurality of data switching circuit selectively connects one of a corresponding one of said sense amplifier circuits and said sense amplifier switching circuit to said data input/output buffer.

3. A semiconductor memory as set forth in claim 2, which further comprises: a first control circuit for outputting a first switching signal for switching said sense amplifier switching circuit, and for causing said sense amplifier switching circuit to select one of said redundant sense amplifier circuits corresponding to said redundant cell array identified by said set number, when said address comparator circuit detects that said input address is coincident with said defective address held in said defective address storing circuit; and a second control circuit for outputting a second switching signal for individually switching said plurality of data switching circuits, and for causing one of said plurality of said data switching circuits corresponding to said defective address to select said sense amplifier switching circuit, when said address comparator circuit detects that said input address is coincident with said defective address held in said defective address storing circuit.

4. A semiconductor memory as set forth in claim 1, wherein said defective address storing circuit comprises: an electrically storage circuit for electrically holding a defective address found in a certain defect inspiring process; and a fixed storage circuit for transferring and fixedly storing at least part of said defective address after a plurality of defect inspecting processes.

5. A semiconductor memory comprising: a memory cell array having electrically rewritable memory cells, said memory cell array being divided into a plurality of banks which are able to be accessed independently of each other; at least one redundant column cell array provided in each of said banks for relieving a defective memory cell of said memory cell array; a decoding circuit provided in each of said banks; a first address bus line for data reading, which is provided commonly for each of said banks; a second address bus line for data writing or erasing, which is provided commonly for each of said banks; a first data bus line for data reading, which is provided commonly for each of said banks; a second data bus line for data writing or erasing, which is provided commonly for each of said banks; a plurality of first sense amplifier circuits, connected to said first data bus line, for detecting and amplifying read data of said memory cell array in parallel; a plurality of second sense amplifier circuits, connected to said second data bus line, for detecting and amplifying verify read data of said memory cell array in parallel; a busy signal circuit, provided in each of said banks, for outputting a busy signal indicating whether an assigned bank is selected as a data write or erase mode or a read mode, said busy signal being used for controlling the selective connection of said first and second address bus lines and for controlling the selective connection of said first and second data bus lines; a defective address storing circuit for storing an input/output terminal, to and from which a defective address of said memory cell array and data corresponding to said defective address are inputted and outputted; a first redundant sense amplifier circuit which is provided so as to correspond to said redundant column cell array and which is connected to said first data bus line for detecting and amplifying read data of said redundant column cell array; a second redundant sense amplifier circuit which is provided so as to correspond to said redundant column cell array and which is connected to said second data bus line for detecting and amplifying verify read data of said redundant column cell array; a first address orator circuit for detecting the coincidence of an address, which is supplied to said first address bus line in a data read operation, with said defective address held in said defective address storing circuit; a second address comparator circuit for detecting the coincidence of an address, which is supplied to said second address bus line in a data write or erase operation, with said defective address held in said defective address storing circuit; a first switching circuit for replacing a part of the output of said plurality of first sense amplifier circuits with the output of said first redundant sense amplifier circuit, on the basis of a coincidence detection output of said first address comparator circuit; and a second switching circuit for replacing a part of the output of said plurality of second sense amplifier circuits with the output of said second redundant sense amplifier circuit, on the basis of a coincidence detection output of said second address comparator circuit.

6. A semiconductor memory as set forth in claim 5, wherein one redundant column cell array, which is the same as said redundant column cell array, is provided in each of said banks.

7. A semiconductor memory as set forth in claim 5, wherein a plurality of redundant column cell arrays, each of which is the same as said redundant column cell array, are provided in each of said banks; said first switching circuit comprises a single first sense amplifier, and a plurality of first data switching circuits provided so as to correspond to said plurality of first sense amplifier circuits; said first sense amplifier switching circuit selectively connects one of said plurality of first redundant sense amplifier circuits to said plurality of first data switching circuits; said plurality of first data switching circuits selectively connects one of a corresponding one of said plurality of sense amplifier circuits and said first sense amplifier switching circuit to a data buffer; said second switching circuit comprises a single second sense amplifier switching circuit, and a plurality of second data switching circuit provided so as to correspond to said plurality of second sense amplifier circuits; said second sense amplifier switching circuit selectively connects one of said plurality of second redundant sense amplifier circuit to said plurality of second data switching circuits; and said plurality of second data switching circuit selectively connects one of a corresponding one of said plurality of second data switching circuits and said second sense amplifier switching circuit to a determining circuit.

8. A semiconductor memory as set forth in claim 5, wherein said defective address storing circuit comprises: an electrically storage circuit for electrically holding a defective address found in a certain defect inspecting process; and a fixed storage circuit for transferring and fixedly storing at least part of said defective address after a plurality of defect inspecting processes.

9. A semiconductor memory comprising: a memory cell array having electrically rewritable memory cells, said memory cell array being divided into a plurality of banks which are able to be accessed independently of each other; a redundant cell array block provided in each of said banks for relieving a defective memory cell of said memory cell array; decoding circuits provided in said memory cell array and said redundant cell array block in each of said banks, respectively; a first address bus line for data reading, which is provided commonly for each of said banks; a second address bus line for data writing or erasing, which is provided commonly for each of said banks; a busy signal circuit, provided in each of said banks, for outputting a busy signal indicating whether an assigned bank is selected as a data write or erase mode or a read mode; an address line switching circuit for connecting one of said first and second address bus lines to said memory array and redundant cell array block of each of said banks, in accordance with said busy signal; a defective block address storing circuit for storing a defective address of said memory cell array; a first address comparator circuit for comparing an address, which is supplied to said first address bus line, with said defective block address, which has been held in said defective address storing circuit, in a data read operation to output a first coincidence detection signal when both are coincide with each other; a second address comparator circuit for comparing an address, which is supplied to said second address bus line, with said defective block address, which has been held in said defective address storing circuit, in a data write or erase operation to output a second coincidence detection signal when both are coincide with each other; and a hit address switching circuit for causing one of said memory cell array and said redundant cell array block to be active and the other to be inactive, in accordance with said first and second coincident detection signals, in each of said banks.

10. A semiconductor memory as set forth in claim 9, wherein said memory cell array of each of said banks comprises a plurality of cores, each of which comprises a set of blocks, each of which is the minimum unit for data erase, and said redundant cell array block of each of said banks comprises one core or a plurality of cores; and which further comprises core decoders, connected to said first and second address bus lines, respectively, for selecting cores on the basis of core addresses inputted ran said first and second address bus lines, and for controlling the activity and inactivity of said decoding circuits in each of said banks on the basis of the outputs thereof.

11. A semiconductor memory as set forth in claim 10, wherein said defective address storing circuit stores defective block addresses, and core addresses of spare blocks, which are to be substituted for blocks of said defective block addresses; said core decoders decodes a corresponding one of said core addresses of said spare block when one of said defective addresses; and said defective blocks of a certain core in each of said banks are able to be replaced with said spares of an optional core.

12. A semiconductor memory as set forth in claim 9, wherein at least one of said plurality of banks has a capacity which is different from that of the other of said plurality of banks, and the capacity ratio of said redundant cell array block in one of said banks having a smaller capacity to said memory cell array is set to be greater than the capacity ratio of said redundant cell array block in the other of said banks having a greater capacity to said memory cell array.

13. A semiconductor memory as set forth in claim 9, wherein said defective address storing circuit comprises: an electrically storage circuit for electrically holding a defective address found in a certain defect inspecting process; and a fixed storage circuit for transferring and fixedly storing at least part of said defective address after a plurality of defect inspecting processes.

14. A semiconductor memory comprising: a memory cell array having electrically rewritable memory cells, said memory cell array being divided into a plurality of banks which are able to be accessed independently of each other, each of said banks having a plurality of cores, each of said cores comprising a set of blocks, each of which is the minis unit for data erase; a redundant cell array block, which has one or more cores provided independently of each of said banks, for relieving a defective memory cell of said memory cell array; a first decoding circuit provided in said memory cell array in each of said banks; a second decoding circuit provided in said redundant cell array block; a first address bus line for data reading, which is provided commonly for each of said banks; a second address bus line for data writing or erasing, which is provided commonly for each of said banks; a busy signal circuit, provided in each of said banks, for outputting a busy signal indicating whether an assigned bank is selected as a data write or erase mode or a read mode; a first address line switching circuit, provided in each of said banks, for connecting one of said first and second address bus lines to said memory array of each of said banks, in accordance with said busy signal; a second address line switching circuit, provided in said redundant cell array block, for connecting said first and second address bus lines to said redundant cell array block; a defective address storing circuit for storing a defective address of said memory cell array; a first address comparator circuit for comparing an address, which is supplied to said first address bus line, with said defective block address, which has been held in said defective address storing circuit, in a data read operation to output a first coincidence detection signal when both are coincide with each other; a second address comparator circuit for comparing an address, which is supplied to said second address bus line, with said defective block address, which has been held in said defective address storing circuit, in a data write or erase operation to output a second coincidence detection signal when both are coincide with each other; a first core decoder, which is provided in each of said banks and which is activated when said first and second address comparator circuits do not output said coincidence detection signal, for decoding a core address of addresses, which are supplied to said first and second address bus line, to supply the decoded core address to said memory cell array; a core switching circuit for selecting an output of said first core decoder in accordance with said busy signal outputted ran said busy signal circuit, to supply the selected output to said memory cell array; and a second core decoder, which is provided in said redundant cell array block and which is activated when said first and second address comparator circuits output said coincidence detection signal, for decoding a core address of addresses, which are supplied to said first and second address bus lines, to supply the decoded core address to said redundant cell array block.

15. A semiconductor memory comprising: a memory cell array having electrically rewritable memory cells, said memory cell array also comprising a plurality of blocks, each of which defines a range of memory cells serving as the minimum unit for data erase; a redundant cell array for relieving a defective memory cell of said memory cell array; a decoding circuit for selecting a memory cell of said memory cell array; a defective address storing circuit for storing a defective address of said memory cell array; and an address comparator circuit for detecting the coincidence of an input address with said defective address which has been held in said defective address storing circuit, wherein a defective row of said memory cell array is replaced with said redundant cell array, and said decoding circuit has a row decoder for supplying 0 V to a defective word line, which is a word line corresponding to said defective address, of a block to be erased in a data erase operation, a negative voltage to other word lines, and 0 V to all of word lines in blocks other than said block to be erased, to allow said defective word line to be replaced every block of said memory cell array.

16. A semiconductor memory as set forth in claim 15, wherein said defective address storing circuit stores a defective row address identifying a defective word line, and a block address; in a data read operation, said raw decoder is controlled by an output of said address comparator circuit so that said memory cell array is inactive and said redundant cell array is active; and in a data erase operation, said raw decoder decodes said defective raw address and block address, which are read out from said defective address storing circuit, to apply 0 V to said defective word line of the selected block to be erased, and a negative voltage to other word lines.

17. A semiconductor memory as set forth in claim 15, wherein said row decoder has a latch circuit in each row, and a latch circuit of a non-defective row latches selection information by the selection of all of row addresses prior to a data erase operation, and in a data erase operation, a negative voltage is applied to a word line of said non-defective row on the basis of said selection information of said latch circuit, and 0 V is applied to a word line of a defective row.

18. A semiconductor memory comprising: a memory cell array; a redundant cell array for relieving a defective cell of said memory cell array; a defective address storing circuit for storing a defective address of said memory cell array; and an address comparator circuit for detecting the coincidence of an input address with said defective address, which has been held in said defective address storing circuit, to replace said defective cell of said memory cell array with said redundant cell array, and wherein said defective address storing circuit comprises: an electrically storage circuit for electrically holding a defective address found in a certain defect inspecting process; and a fixed storage circuit for transferring and fixedly storing at least part of said defective address after a plurality of defect inspecting processes.

19. A semiconductor memory as set forth in claim 18, wherein said electrically storage circuit comprises an electrically rewritable nonvolatile memory cell.

20. A semiconductor memory as set forth in claim 18, wherein said electrically storage circuit comprises a latch circuit.

Description:

RELATED APPLICATION

[0001] This application claims the benefit of priority under 35U.S.C. § 119 of Japanese Patent Applications Nos. H11-156255, filed on Jun. 3, 1999, and 2000-65398, filed on Mar. 9, 2000, the entire contents of which are incorporated by reference herein.

BACKGROUND OF THE INVENTION

[0002] 1. Field of The Invention

[0003] The present invention relates generally to an electrically rewritable semiconductor memory, such as an EEPROM. More specifically, the invention relates to a semiconductor memory having a redundant circuit for replacing a defective memory cell.

[0004] 2. Description of The Related Background Art

[0005] In typical large scale semiconductor memories, a redundant circuit system for relieving a device having a certain range of defective memory cells is adopted in order to improve producing yields. The redundant circuit systems include three types, i.e., a column redundant circuit for replacing a defective bit line with a spare bit line, a row redundant circuit for replacing a defective word line with a spare word line, and a combination thereof.

[0006] A memory of a redundant circuit system has a defective address storing circuit, such as a fuse circuit, for nonvolatilisably storing a defective address. Then, the coincidence of an input address with a defective address is detected to output a coincidence detection output. In response to the coincidence detection output, the memory cell of the defective address is replaced with a memory cell of a redundant circuit.

[0007] However, in conventional EEPROMs, the relief efficiency using the redundant circuit is not high. Because it is not possible to cope with a plurality of defective columns or rows even if redundant circuits corresponding to one column or one row are arranged at the end portion of a memory cell array. In addition, even if redundant circuits corresponding to one column or one row are arranged at the end portion of the memory cell, there is a strong possibility that the redundant circuits themselves at the end portion of the cell array will be defective. This also lowers the relief efficiency.

SUMMARY OF THE INVENTION

[0008] It is therefore an object of the present invention to provide a semiconductor memory capable of effectively relieving a plurality of defective columns and a defect in a boundary region in column directions.

[0009] It is another object of the present invention to provide a semiconductor memory of the RWW specification capable of efficiently columns in each bank.

[0010] It is a further object of the present invention to provide a semiconductor memory capable of effectively relieving a defective row by preventing any useless pass current paths from being produced in a data erase operation.

[0011] It is a still further object of the present invention to provide a semiconductor memory having a defective address storing circuit capable of shortening time in a defect inspection process.

[0012] The present invention is effective in the application to EEPROMs as well as other semiconductor memories, such as DRAMs.

[0013] In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor memory comprises:

[0014] a memory cell array having electrically rewritable memory cells; a plurality of redundant column cell arrays for relieving a defective memory cell in the memory cell array;

[0015] a decoding circuit for selecting a memory cell of the memory cell array;

[0016] a plurality of sense amplifier circuits for detecting read data of the memory cell array and for latching write data;

[0017] data input/output buffers provided between each of the sense amplifier circuits and a corresponding one of data input/output terminals;

[0018] a defective address storing circuit for storing a defective address of the memory cell array, an input/output terminal to and from which data corresponding to the defective address are inputted and outputted, and a set number for identifying one of the plurality of redundant column cell arrays, which is to be substituted so as to correspond to the input/output terminal;

[0019] a plurality of redundant sense amplifier circuits for detecting read data of the plurality of redundant column cell arrays and for latching write data;

[0020] an address comparator circuit for outputting a coincidence detection signal when an input address is coincident with the defective address held in the defective address storing circuit; and

[0021] a switching circuit which is controlled by the coincidence detection signal for selectively connecting one of the sense amplifier corresponding to the defective address in the plurality of sense amplifier circuits or one of the redundant sense amplifier circuits identified by the set number in the plurality of redundant sense amplifier circuit, to the data input/output buffer.

[0022] According to another aspect of the present invention, a semiconductor memory comprises:

[0023] a memory cell array having electrically rewritable memory cells, the memory cell array being divided into a plurality of banks which are able to be accessed independently of each other;

[0024] at least one redundant column cell array provided in each of the banks for relieving a defective memory cell of the memory cell array;

[0025] a decoding circuit provided in each of the banks;

[0026] a first address bus line for data reading, which is provided commonly for each of the banks;

[0027] a second address bus line for data writing or erasing, which is provided commonly for each of the banks;

[0028] a first data bus line for data reading, which is provided commonly for each of the banks;

[0029] a second data bus line for data writing or erasing, which is provided commonly for each of the banks;

[0030] a plurality of first sense amplifier circuits, connected to the first data bus line, for detecting and amplifying read data of the memory cell array in parallel;

[0031] a plurality of second sense amplifier circuits, connected to the second data bus line, for detecting and amplifying verify read data of the memory cell array in parallel;

[0032] a busy signal circuit, provided in each of the banks, for outputting a busy signal indicating whether an assigned bank is selected as a data write or erase mode or a read mode, the busy signal being used for controlling the selective connection of the first and second address bus lines and for controlling the selective connection of the first and second data bus lines;

[0033] a defective address storing circuit for storing an input/output terminal, to and from which a defective address of the memory cell array and data corresponding to the defective address are inputted and outputted;

[0034] a first redundant sense amplifier circuit which is provided so as to correspond to the redundant column cell array and which is connected to the first data bus line for detecting and amplifying read data of the redundant column cell array;

[0035] a second redundant sense amplifier circuit which is provided so as to correspond to the redundant column cell array and which is connected to the second data bus line for detecting and amplifying verify read data of the redundant column cell array;

[0036] a first address comparator circuit for detecting the coincidence of an address, which is supplied to the first address bus line in a data read operation, with the defective address held in the defective address storing circuit;

[0037] a second address comparator circuit for detecting the coincidence of an address, which is supplied to the second address bus line in a data write or erase operation, with the defective address held in the defective address storing circuit;

[0038] a first switching circuit for replacing a part of the output of the plurality of first sense amplifier circuits with the output of the first redundant sense amplifier circuit, on the basis of a coincidence detection output of the first address comparator circuit; and

[0039] a second switching circuit for replacing a part of the output of the plurality of second sense amplifier circuits with the output of the second redundant sense amplifier circuit, on the basis of a coincidence detection output of the second address comparator circuit.

[0040] According to a further aspect of the present invention, a semiconductor memory comprises:

[0041] a memory cell array having electrically rewritable memory cells, the memory cell array being divided into a plurality of banks which are able to be accessed independently of each other;

[0042] a redundant cell array block provided in each of the banks for relieving a defective memory cell of the memory cell array;

[0043] decoding circuits provided in the memory cell array and the redundant cell array block in each of the banks, respectively;

[0044] a first address bus line for data reading, which is provided commonly for each of the banks;

[0045] a second address bus line for data writing or erasing, which is provided commonly for each of the banks;

[0046] a busy signal circuit, provided in each of the banks, for outputting a busy signal indicating whether an assigned bank is selected as a data write or erase mode or a read mode;

[0047] an address line switching circuit for connecting one of the first and second address bus lines to the memory array and redundant cell array block of each of the banks, in accordance with the busy signal;

[0048] a defective block address storing circuit for storing a defective address of the memory cell array;

[0049] a first address comparator circuit for comparing an address, which is supplied to the first address bus line, with the defective block address, which has been held in the defective address storing circuit, in a data read operation to output a first coincidence detection signal when both are coincide with each other;

[0050] a second address comparator circuit for comparing an address, which is supplied to the second address bus line, with the defective block address, which has been held in the defective address storing circuit, in a data write or erase operation to output a second coincidence detection signal when both are coincide with each other; and

[0051] a hit address switching circuit for causing one of the memory cell array and the redundant cell array block to be active and the other to be inactive, in accordance with the first and second coincident detection signals, in each of the banks.

[0052] According to a still further aspect of the present invention, a semiconductor memory comprises:

[0053] a memory cell array having electrically rewritable memory cells, the memory cell array being divided into a plurality of banks which are able to be accessed independently of each other, each of the banks having a plurality of cores, each of the cores comprising a set of blocks, each of which is the minimum unit for data erase;

[0054] a redundant cell array block, which has one or more cores provided independently of each of the banks, for relieving a defective memory cell of the memory cell array;

[0055] a first decoding circuit provided in the memory cell array in each of the banks;

[0056] a second decoding circuit provided in the redundant cell array block;

[0057] a first address bus line for data reading, which is provided commonly for each of the banks;

[0058] a second address bus line for data writing or erasing, which is provided commonly for each of the banks;

[0059] a busy signal circuit, provided in each of the banks, for outputting a busy signal indicating whether an assigned bank is selected as a data write or erase mode or a read mode;

[0060] a first address line switching circuit, provided in each of the banks, for connecting one of the first and second address bus lines to the memory array of each of the banks, in accordance with the busy signal;

[0061] a second address line switching circuit, provided in the redundant cell array block, for connecting the first and second address bus lines to the redundant cell array block;

[0062] a defective address storing circuit for storing a defective address of the memory cell array;

[0063] a first address comparator circuit for comparing an address, which is supplied to the first address bus line, with the defective block address, which has been held in the defective address storing circuit, in a data read operation to output a first coincidence detection signal when both are coincide with each other;

[0064] a second address comparator circuit for comparing an address, which is supplied to the second address bus line, with the defective block address, which has been held in the defective address storing circuit, in a data write or erase operation to output a second coincidence detection signal when both are coincide with each other;

[0065] a first core decoder, which is provided in each of the banks and which is activated when the first and second address comparator circuits do not output the coincidence detection signal, for decoding a core address of addresses, which are supplied to the first and second address bus line, to supply the decoded core address to the memory cell array;

[0066] a core switching circuit for selecting an output of the first core decoder in accordance with the busy signal outputted from the busy signal circuit, to supply the selected output to the memory cell array; and

[0067] a second core decoder, which is provided in the redundant cell array block and which is activated when the first and second address comparator circuits output the coincidence detection signal, for decoding a core address of addresses, which are supplied to the first and second address bus lines, to supply the decoded core address to the redundant cell array block.

[0068] According to another aspect of the present invention, a semiconductor memory comprises:

[0069] a memory cell array having electrically rewritable memory cells, the memory cell array also comprising a plurality of blocks, each of which defines a range of memory cells serving as the minimum unit for data erase;

[0070] a redundant cell array for relieving a defective memory cell of the memory cell array;

[0071] a decoding circuit for selecting a memory cell of the memory cell array;

[0072] a defective address storing circuit for storing a defective address of the memory cell array; and

[0073] an address comparator circuit for detecting the coincidence of an input address with the defective address which has been held in the defective address storing circuit,

[0074] wherein a defective raw of the memory cell array is replaced with the redundant cell array, and

[0075] the decoding circuit has a row decoder for supplying 0 V to a defective word line, which is a word line corresponding to the defective address, of a block to be erased in a data erase operation, a negative voltage to other word lines, and 0 V to all of word lines in blocks other than the block to be erased, to allow the defective word line to be replaced every block of the memory cell array

[0076] According to further aspect of the present invention, a semiconductor memory comprises:

[0077] a memory cell array;

[0078] a redundant cell array for relieving a defective cell of the memory cell array;

[0079] a defective address storing circuit for storing a defective address of the memory cell array; and

[0080] an address comparator circuit for detecting the coincidence of an input address with the defective address, which has been held in the defective address storing circuit, to replace the defective cell of the memory cell array with the redundant cell array, and

[0081] wherein the defective address storing circuit comprises:

[0082] an electrically storage circuit for electrically holding a defective address found in a certain defect inspecting process; and

[0083] a fixed storage circuit for transferring and fixedly storing at least part of the defective address after a plurality of defect inspecting processes.

BRIEF DESCRIPTION OF THE DRAWINGS

[0084] The present invention will be understood more fully from the detailed description given herebelow and from the accompanying drawings of the preferred embodiments of the invention. However, the drawings are not intended to imply limitation of the invention to a specific embodiment, but are for explanation and understanding only.

[0085] In the drawings:

[0086] FIG. 1 is a block diagram of a preferred embodiment of an EEPROM having redundant column cell arrays according to the present invention;

[0087] FIG. 2 is a diagram showing the construction of a memory cell array in this preferred embodiment;

[0088] FIG. 3 is a block diagram of a second preferred embodiment of an EEPROM of the RWW specification having a single redundant column cell array according to the present invention;

[0089] FIG. 4A is a block diagram of an address supply part in the EEPROM of FIG. 3 ;

[0090] FIG. 4B is a block diagram of a second preferred embodiment of an EEPROM of the RWW specification having a plurality of redundant column cell arrays according to the present invention;

[0091] FIG. 4C is a block diagram of an address supply part in the EEPROM of FIG. 4B ;

[0092] FIG. 5 is a block diagram of another preferred embodiment of an EEPROM of the RWW specification having a redundant column cell array according to the present invention;

[0093] FIG. 6 is a block diagram of an address supply part in this preferred embodiment;

[0094] FIG. 7 is a block diagram of another preferred embodiment of an EEPROM of the RWW specification having a redundant column cell array according to the present invention;

[0095] FIG. 8 is a block diagram of another preferred embodiment of an EEPROM of the RWW specification having a redundant column cell array according to the present invention;

[0096] FIG. 9 is a block diagram of another preferred embodiment of an EEPROM of the RWW specification having a redundant column cell array according to the present invention;

[0097] FIG. 10 is a diagram showing the replacement of a block with a redundant cell array block in the preferred embodiments of FIGS. 5 and 7 ;

[0098] FIG. 11 is a diagram showing the replacement of a block with a redundant cell array block in the preferred embodiment of FIG. 8 ;

[0099] FIG. 12 is a diagram showing the replacement of a block with a redundant cell array block in the preferred embodiment of FIG. 9 ;

[0100] FIG. 13 is a diagram showing the replacement of a block with a redundant cell array block in a modified preferred embodiment of the preferred embodiments of FIGS. 5 and 7 ;

[0101] FIG. 14 is a block diagram of a preferred embodiment of an EEPROM having a redundant row cell array according to the present invention;

[0102] FIG. 15 is a block diagram of an address supply part in this preferred embodiment;

[0103] FIG. 16 is a diagram showing the details of a principal part in this preferred embodiment;

[0104] FIG. 17 is a diagram showing the construction of a row main decoder in this preferred embodiment;

[0105] FIG. 18 is a diagram showing the construction of a word line selecting drive circuit in this preferred embodiment;

[0106] FIG. 19 is a diagram showing the construction of a row main decoder of another preferred embodiment of an EEPROM having a redundant row cell array according to the present invention;

[0107] FIG. 20 is a flow chart showing the first half of a sequence of an automatic data erase operation in the preferred embodiment having the row main decoder shown in FIG. 19 ;

[0108] FIG. 21 is a flow chart showing the second half of the sequence;

[0109] FIG. 22 is a block diagram of another preferred embodiment of an EEPROM of the RWW specification having a redundant row cell array according to the present invention;

[0110] FIG. 23 is a schematic diagram showing another preferred embodiment of a semiconductor memory according to the present invention;

[0111] FIG. 24 is a block diagram of a ROM fuse circuit in this preferred embodiment;

[0112] FIG. 25 is a diagram showing a die sort flow in this preferred embodiment, as compared with that in a conventional case;

[0113] FIG. 26 is a schematic diagram showing another preferred embodiment of a semiconductor memory according to the present invention; and

[0114] FIG. 27 is a diagram showing the construction of a latch for use in this preferred embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0115] Referring now to the accompanying drawings, the preferred embodiments of the present invention will be described below.

[0116] (First Preferred Embodiment)

[0117] FIG. 1 shows the construction of a first preferred embodiment of an EEPROM having a column redundant circuit according to the present invention. A memory cell array 101 comprises a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cells MC, each of which is arranged at a corresponding one of the intersections of the bit and word lines, as shown in FIG. 2 . Each of the memory cells MC has a MOS transistor structure having a floating gate and a control gate stacked thereon, and is designed to nonvolatilisably store, as binary data, the difference in threshold due to the presence of charge injection into the floating gate. FIG. 2 shows an example of a NOR type EEPROM. Also in preferred embodiments which will be described later, the same memory cell array structure will be used.

[0118] In a data write operation in a memory cell of this type, a positive voltage is applied to a selected bit line BL, and a higher positive voltage than that applied to the bit line is applied to a selected word line WL, so that electrons are injected into a floating gate by the hot electron injection. The state that electrons are injected into the floating gate to raise the threshold is, e.g., data “0”. In a data erase operation, a range including continuous word lines WL is used as a block serving as the minimum unit for erase, and a negative voltage is applied to all of the word lines every block to emit the electrons of the floating gate to a substrate. The state that the electrons of the floating gate are thus emitted to lower the threshold voltage is, e.g., data “1”.

[0119] With respect to addresses acquired by an address buffer 106 , a row address and a column address are decoded, via a pre-decoder 107 , by means of a row decoder 102 and a column decoder 103 , respectively. By these decoded outputs, the word line selection and bit line selection of the memory cell array 101 are carried out. The bit line data selected by the column decoder 103 are detected and amplified by means of a sense amplifier circuit 104 . In a data write operation, the sense amplifier circuit 104 has the function of latching data acquired via a data buffer 113 from an input/output terminal. In the shown embodiment, a 16-bit parallel read/write operation is intended to be carried out, and 16 sense amplifier circuits 104 are provided for 16 input/output terminals to carry out data transfer to 16 bit lines BL.

[0120] The usual memory cell array 101 is provided with redundant column cell arrays 201 ( 201 a through 201 c ) including spare bit Lines SBL corresponding to a plurality of columns (three columns in the shown embodiment) in order to replace defective bit lines therein. Redundant sense amplifier circuits 105 are connected to the redundant column cell arrays 201 , respectively. A sense amplifier switching circuit 114 is designed to select one of the redundant sense amplifier circuits 105 . In addition, a data switching circuit 112 is provided for switching the selected redundant sense amplifier circuit 105 to one of the 16 sense amplifier circuits 104 to connect it to a data input/output buffer 113 .

[0121] That is, in this preferred embodiment, data in the redundant column cell arrays 201 and the selected data in the memory cell array 101 are simultaneously read out, and when a defective column is selected, an output switching control for using one of the redundant sense amplifier circuits 105 , which is connected to one of the redundant column cell arrays 201 , in place of the sense amplifier circuit 104 corresponding to the defective column is carried out. For this substitution control, there are provided a defective address storing circuit 108 , an address comparator circuit 109 , a defective I/O decoder 110 and a block set number decoder 111 .

[0122] The defective address storing circuit 108 is, e.g., a fuse circuit, and stores a defective column address which has been detected by a test, data (4 bits in this preferred embodiment) for an input/output terminal, to and from which data corresponding to the defective column address should be inputted and outputted, and a set number (2 bits in this preferred embodiment) in a redundant column cell array 201 which corresponds to the input/output terminal and which should be substituted. The address comparator circuit 109 detects the coincidence of an input address with the defective address which has been held in the defective address storing circuit 108 . When the coincidence is detected, the defective I/O decoder 110 decodes an I/O terminal corresponding to the stored defective address on the basis of the detection signal, and outputs hit signals HIT< 0 : 15 >. The hit signals HIT< 0 : 15 > mean a set of hit signals HIT< 0 >through HIT< 15 >.

[0123] Assuming that the three redundant sense amplifier circuits 105 are S/A (RD 0 ), S/A (RD 1 ) and S/A (RD 2 ), it is assumed that the logic of the block set number decoder 111 has 00=S/A (RD 0 ), 01 =S/A (RD 0 ), 10=S/A (RD 1 ) and 11=S/A (RD 2 ). By switching the sense amplifier switching circuit 114 in such a logic, it is possible to select one of the redundant sense amplifier circuits 105 . At this time, if the logic of the block set number decoder 111 is set so that HIT< 0 : 15 > is 0-fixed at 00, this can be used as an enable bit.

[0124] Specifically, the case of block set number “01” will be described as an example. The coincidence of a defective address with an inputted internal address is detected by the address comparator circuit 109 . When no coincidence is detected, the output HIT< 0 : 15 > of the defective I/O decoder 110 is 0-fixed. At this time the data switching circuit 112 derives the output of the original sense amplifier circuit 104 to transfer the output to the data buffer 113 . When the coincidence is detected by the address comparator circuit 109 , assuming that the defect IO terminal information stored in the defective address storing circuit 108 is, e.g., “0101” (=IO 5 ), the hit signal HIT< 5 > has “1”, and the hit signals HIT< 0 : 4 > and HIT< 6 : 15 > have “0”. On the other hand, by the block set number “01”, the sense amplifier circuit S/A (RD 0 ) of the redundant sense amplifier circuits 105 is selected. The output of this sense amplifier circuit S/A (RD 0 ) enters the data switch circuit 112 to be selected by the hit signal HIT< 5 > to be transferred to the data input/output buffer 113 . The other data switching circuits 112 of IO=0˜4 and IO=6˜15 have hit signals HIT< 0 : 4 > and HIT< 6 : 15 >=“0”, so that the output of the original sense amplifier circuit 104 is selected.

[0125] As described above, according to this preferred embodiment, each of the redundant sense amplifier circuits 105 is provided for the corresponding one of the redundant column cell arrays 201 for three columns, and 16+6-bit data are simultaneously read out in a data read operation. Then, the substitution for defective data corresponding to the defective address is carried out by the sense amplifier switching circuit 114 and the data switching circuit 122 . Thus, it is possible to relieve a plurality of defective columns. In addition, in this preferred embodiment, the redundant circuits for the plurality of columns are used, so that the relief efficiency is high.

[0126] Moreover, in the case of this preferred embodiment, the output of the redundant column cell array is read out simultaneously with the read-out of normal memory cell data including the defective address, and the read output of the defective column address is switched by the output of the redundant cell array. Thus, the read output of the redundant cell array is not delayed from the read output of the normal cell array.

[0127] In addition, the outputs of the plurality of redundant sense amplifier circuits 105 are switched by the sense amplifier circuit 114 to supply the output of one of the redundant sense amplifier circuits 105 to the data switching circuit 112 . That is, the outputs of the redundant sense amplifier circuits 105 are supplied to the data buffer 113 by means of the two-stage switching circuits of the sense amplifier switching circuit 114 and data switching circuit 112 . Therefore, the number of buses between the sense amplifier switching circuit 114 and the data switching circuit 112 can be one. That is, the number of buses between the sense amplifier switching circuit and the data switching circuit 112 can be decreased as cared with when the sense amplifier switching circuit 114 is not provided.

[0128] Furthermore, the number of the redundant columns should not be limited to three, but it may be more. In that case, the redundant sense amplifier circuit may be provided for each of the redundant columns to use the circuit system in the above described preferred embodiment.

[0129] (Second Preferred Embodiment)

[0130] FIGS. 3 and 4 A show a preferred embodiment of an EEPROM of the RWW (Read While Write) specification having a column redundant circuit according to the present invention. In the EEPROM of the RWW specification, a memory cell array is divided into at least two banks so that a data write or erase operation can be carried out in one bank while a data read operation is carried out in the other bank. In the embodiment of FIG. 3, a memory cell array 101 comprises two banks BANK 0 and BANK 1 .

[0131] In order to make it possible to simultaneously access the two banks BANK 0 and BANK 1 , each of the banks BANK 0 and BANK 1 is provided with a pre-decoder 301 , a raw decoder 302 and a column decoder 303 . In addition, each of the banks BANK 0 and BANK 1 is provided with a redundant column cell array 304 comprising a single spare bit line. In order to make it possible to carry out a data write or erase operation in one of the two banks BANK 0 and BANK 1 while carrying out a data read operation in the other bank, two systems of address bus lines 305 a, 305 b and data bus lines 306 a, 306 b are provided commonly for the two banks. That is, the address bus line 305 a is provided for carrying out a data read operation, and the address bus line 305 b is provided for carrying out a data write or erase operation. The data bus line 306 a is provided for carrying out a data read operation, and the data bus line 306 b is provided for carrying out a data write or erase operation.

[0132] As shown in FIG. 4A, a data write or erase command is inputted to a control circuit 310 . A write address is received by an address latch when a write command is inputted. Although a data erase operation is carried out every erase block of the memory cell array, an erase block address is set in a block selecting register (not shown) corresponding to a selected block when an erase command is inputted. In a data read operation, an address is supplied to the address bus line 305 a via an address buffer 307 .

[0133] An address switching circuit 311 selects the address, which has been latched by the address latch 308 , in a data write operation, and the address, which is sequentially incremented from an address counter 309 , in a data erase operation, to supply the selected address to the address bus line 305 b.

[0134] As shown in FIG. 3 , each of the banks BANK 0 and BANK 1 is provided with a busy register 315 for indicating the operation mode of the selected bank. With respect to the bank to be written or erased, “H” is set in the busy register 315 by a command from the control circuit 310 . With respect to the bank which is not to be written or erased, the busy register 315 holds “L”.

[0135] Each of the banks BANK 0 and BANK 1 has a data line switching circuit (DLSW 1 ) 316 a for connecting the bank to the reading data bus line 306 a, and a data line switching circuit (DLSW 2 ) 316 b for connecting the bank to the writing or erasing data bus line 306 b. In the shown embodiment, the 16-bit parallel read operation is carried out, so that the number of each of the data line switching circuits 316 a and 316 b is 16. Similarly, also with respect to the redundant column cell array 304 , two systems of data line switching circuits 317 a and 317 b are provided.

[0136] The on-off of these two systems of data line switching circuits is controlled by data of the busy register 315 . That is, if the output of the busy register 315 has “H”, the data line switching circuits 316 b and 317 b are turned on, so that the bank is connected to the writing or erasing data bus line 306 b. If the output of the busy register 315 has “L”, the date line switching circuits 316 a and 317 a are turned on, so that the bank is connected to the writing or erasing data bus line 306 a.

[0137] Similarly, also with respect to the two systems of address bus lines 305 a and 305 b, each of the banks is provided with two systems of address line switching circuits (AddSW 1 , AddSW 2 ) 318 a and 318 b. These address line switching circuits 318 a and 318 b are also controlled by the busy register 315 . That is, if the output of the busy register 315 has “H”, the address line switching circuit 318 b is turned on, so that the address of the writing or erasing address bus vine 305 b is supplied to the pre-decoder 301 . If the output of the busy register 315 has “L”, the address line switching circuit 318 a is turned on, so that the address of the reading address bus line 305 a is supplied to the pre-decoder 301 .

[0138] A sense amplifier circuit 319 a for sensing read data is connected to the reading data bus line 306 a. (A sense amplifier circuit 319 b for use in a verify read in a writing or erasing operation is connected to the writing or erasing data bus line 306 b. In the shown embodiment, the 16-bit parallel operation is carried out, so that the number of each of the sense amplifier circuits 319 a and 319 b is 16. In addition, in order to read the output of the redundant column cell array, each of the data bus line 306 a and 306 b is provided with a single redundant sense amplifier circuit 320 a or 320 b.

[0139] In order to replace one of the outputs of the sense amplifier circuits 3 l 9 a with the output of the redundant sense amplifier circuit 320 a when a defective column address is selected in a data read operation, a data switching circuit 321 a is provided. This data switching circuit 321 a is controlled by a bit signal HITa< 0 : 15 > generated by the detection of a defective address. Similarly, in order to replace one of the outputs of the sense amplifier circuits 319 b with the output of the redundant sense amplifier circuit 320 b when a defective column address is selected in a verify read operation, a data switching circuit 321 b is provided. This data switching circuit 321 b is controlled by a bit signal HITb< 0 : 15 > generated by the detection of a defective address.

[0140] Then, in a usual data read operation, read data are outputted to the outside via a data buffer 323 . In addition, read data in the verify read operation are fed to a determining circuit 322 , in which a verify determination is carried out.

[0141] As shown in FIG. 4 A, in order to output bit signals HITa and HITb for the substitution for a defective column in a write or erase verify read operation, address comparator circuits 313 a, 313 b and defective I/O decoders 314 a, 314 b are provided so as to correspond to the two systems of address bus lines 305 a and 305 b. The defective column address of each of the banks, and data of an input/output terminal (I/O) corresponding thereto are stored in an address storing circuit 312 . Each of the address comparator circuits 313 a and 313 b detects the coincidence of the address of the address bus lines 305 a and 305 b with the address, which has been held by the storing circuit 312 , in a data read operation and a verify read operation. After the coincidence is detected, hit signals HITa< 0 : 15 > and HITb< 0 : 15 > are outputted in accordance with a defective I/O by means of the defective I/O decoders 314 a and 314 b similar to the preceding preferred embodiment.

[0142] The operation of the substitution for a defective column in this preferred embodiment will be described in detail below.

[0143] In a data read operation, an address acquired from the address buffer 307 is compared with the address of the defective address storing circuit 213 in the address comparator circuit 313 a. If no coincidence is detected, all of hit signals HITa< 0 : 15 > have “0”. Therefore, all of the data switching circuits 321 a select the output of the sense amplifier circuit 319 a, so that the output of the sense amplifier circuit 319 a is inputted directly to the data buffer 323 .

[0144] On the other hand, if the coincident detection is carried out in the address comparator circuit 3 l 3 a and if I/O=15 is defective, the hit signal HITa< 0 > through the hit signal HITa< 14 > of the hit signals HITa< 0 : 15 > have “0”, and the high signal HITa< 15 > thereof has “1”. Thus, in the data switching circuit 321 a, the output of the sense amplifier circuit 319 a of I/O=15 is replaced with the output of the redundant sense amplifier circuit 320 a to be outputted to the data buffer 323 . The outputs of the sense amplifier circuit 319 a other than I/O=15 are inputted directly to the data buffer 323 .

[0145] In a data write or erase operation, an address from the address latch 308 or the address counter 309 is compared with the address of the defective address storing circuit 312 , in the address comparator circuit 313 b. If no coincidence is detected, all of the hit signals HITb< 0 : 15 > have “0”. Therefore, all of the data switching circuits 321 b select the output of the sense amplifier circuit 319 b, so that the output of the sense amplifier circuit 319 b is inputted directly to the determining circuit 322 .

[0146] On the other hand, if the coincident is detected in the address comparator circuit 313 b and if I/O=15 is defective, the hit signal HITb< 0 > through the hit signal HITb< 14 > of the hit signals HITb< 0 : 15 > have “0”, and the high signal HITb< 15 > thereof has “1”. Thus, in the data switching circuit 321 b, the output of the sense amplifier circuit 319 b of I/O=15 is replaced with the output of the redundant sense amplifier circuit 320 b to be outputted to the determining circuit 322 . The outputs of the sense amplifier circuit 319 b other than I/O=15 are inputted directly to the determining circuit 322 .

[0147] As described above, since the EEPROM in this preferred embodiment has the RWW specification, the two systems of address bus lines and data bus lines are provided commonly for the plurality of banks, and the connections of these two systems of address bus lines and data bus lines are switched by a busy signal, so that a data write or erase operation can be carried out in one bank while a data read operation can be carried out in the other bank. Similar to the first preferred embodiment, the output of the redundant column cell array is outputted to the redundant sense amplifier circuit simultaneously with the output of the original memory cell array. Then, two systems of address comparator circuits for detecting the coincidence of the defective address are prepared so as to correspond to the operation modes of two systems, and the output of the sense amplifier circuit is switched in each of the operation modes to realize the substitution for a defective column.

[0148] Furthermore, in this second preferred embodiment, one redundant column cell array 304 has been provided for simple explanation. However, similar to the first preferred embodiment, a plurality of redundant column cell arrays may be prepared to carry out the substitution for a plurality of columns by the same system as that in the first preferred embodiment.

[0149] FIGS. 4B and 4C show the construction of an EEPROM when one memory cell array 101 is provided with three redundant column cell arrays 304 a through 304 c in the second preferred embodiment, which correspond to FIGS. 3 and 4 A, respectively.

[0150] As shown in FIG. 4 B, three sets of data line switching circuits 317 a and 317 b are provided so as to correspond to the three redundant column cell arrays 304 a through 304 c. Each of the data line switch circuits 317 a is connected to the data reading data bus line 306 a, and each of the data line switching circuits 317 b is connected to the data writing or erasing data bus line 306 b.

[0151] The three redundant sense amplifier circuits 324 a through 324 c are connected to the data reading data bus line 306 a. These three redundant sense amplifier circuits 324 a through 324 c detect and amplify the read data of the three redundant column cell arrays 304 a through 304 c, respectively. These three redundant sense amplifier circuits 324 a through 324 c are connected to the sense amplifier switching circuit 114 a via three data bus lines. Moreover, the sense amplifier switching circuit 114 a is connected to each of the data switching circuits 321 a in the wiring form that one data bus line finally branches. This sense amplifier switching circuit 114 a is a circuit for connecting one of data bus lines from the redundant sense amplifier circuits 324 a through 324 c to the data switching circuit 321 a on the basis of a logic signal LGCa outputted from the block set number decoder 111 a (see FIG. 4C ).

[0152] That is, in a data read operation, when a column of the memory cell array 101 is replaced with any one of the redundant cell arrays 304 a through 304 c, one redundant cell array 304 is selected by the sense amplifier switching circuit 114 a. Then, in the data switching circuit 321 a corresponding to a column to be replaced, data from the sense amplifier switching circuit 114 a are outputted to the data buffer 323 in place of data from the sense amplifier circuit 319 a. Thus, the substitution for a defective column in a data read operation is carried out.

[0153] On the other hand, three redundant sense amplifier circuits 325 a through 325 c are connected to the writing or erasing data bus line 306 b. These three redundant sense amplifier circuits 325 a through 325 c detect and amplify the verify read data of the three redundant column cell arrays 304 a through 304 c, respectively. These three redundant sense amplifier circuits 325 a through 325 c are connected to the sense amplifier switching circuit 114 b via three data bus lines. Moreover, the sense amplifier switching circuit 114 b is connected to each of the data switching circuits 321 b in the wiring form that one data bus finally branches. This sense amplifier switching circuit 114 b is a circuit for connecting one of the data bus lines from the redundant sense amplifier circuits 324 a through 324 c to the data switching circuit 321 b on the basis of a logic signal LGCb outputted from the block set number decoder 111 b (see FIG. 4C ).

[0154] That is, in a verify data read operation, when a column of the memory cell array 101 is replaced with any one of the redundant cell arrays 304 a through 304 c, one redundant cell array 3 O 4 is selected by means of the sense amplifier switching circuit 114 b. Then, in the data switching circuit 321 b corresponding to a column to be replaced, data from the sense amplifier switching circuit 114 b are outputted to the determining circuit 322 in place of data from the sense amplifier circuit 319 b. Thus, the substitution for a defective column during a verify data read in a write or erase operation is carried out.

[0155] (Third Preferred Embodiment)

[0156] FIGS. 5 and 6 show a preferred embodiment of an EEPROM of the RWW specification of a block redundant circuit system herein a block which is the minimum unit for data erase in the memory cell array and which is a set of a plurality of memory cells corresponds to a unit for substitution for defect relief. A memory cell array 401 basically has the same construction as those in the first and second preferred embodiments, except that it is divided into at least two banks BANK 0 and BANK 1 similar to the second preferred embodiment. In order to substitute for a defective block in each of the banks of the memory cell array 401 , a redundant cell array block (which will be hereinafter simply referred to as a redundant block) 403 is provided. The redundant block 403 crises one spare block or a plurality of spare blocks.

[0157] In the figure, the memory cell array 401 and the redundant block 403 include a row decoder, a column decoder and a sense amplifier circuit. The memory cell array 401 and the redundant block 403 are provided with pre-decoders 402 and 404 for decoding a row address and column address supplied thereto, respectively.

[0158] Similar to the preceding second preferred embodiment, two systems of address bus lines 305 a and 305 b are provided. In addition, each of the banks BANK 0 and BANK 1 is provided with a busy register 315 and with address line switching circuits 318 a and 318 b which are on-off controlled by the busy register 315 . That is, in a write or erase mode, the address of the address bus line 305 b is simultaneously supplied to the pre-decoders 402 and 404 by the address line switch circuit 318 b. In a read mode, the address of the address bus line 305 a is simultaneously supplied to the pre-decoders 402 and 404 by the address lime switching circuit 318 a.

[0159] The construction of an address supply part shown in FIG. 6 is basically the same as that in the preceding preferred embodiment shown in FIG. 4A . Then, if the output signal lines 411 a and 411 b of two systems of address comparator circuits 313 a and 313 b are provided commonly for the two banks BANK 0 and BANK 1 and if the coincidence with the defective address is detected, hit signals HITa=“H” and HITb=“H” are outputted thereto.

[0160] Each of the banks BANK 0 and BANK 1 is provided with two systems of high address switching circuits 410 a and 410 b. When the hit signals HITa=HITb=“L”, the high address switching circuits 410 a and 410 b cause the pre-decoder 402 on the side of the memory cell array 401 to be active and the pre-decoder 404 on the side of the redundant block to be inactive. Then, when the bit signal HITa=“H”, the high address switching circuit 410 a causes the pre-decoder 402 to be inactive and the pre-decoder 404 to be active. The hit address switching circuit 410 b also controls the activity and inactivity on the sides of the memory cell array 401 and redundant block 403 .

[0161] Also in this preferred embodiment similar to the preceding second preferred embodiment, the reading data bus line 306 a and the writing or erasing data bus line 306 b are provided commonly for each of the banks BANK 0 and BANK 1 . Although addresses have been simultaneously supplied to the memory cell array 401 and the redundant block 403 , when an input address is not coincident with the defective address, the side of the memory cell array 401 is active, and when the input address hits the defective address, the side of the redundant block 403 is active, so that data are read out therefrom. These read data are switched to the reading data bus line 306 a or the verify reading data bus line 306 b in accordance with the operation mode to be outputted.

[0162] As described above, according to this preferred embodiment, the control of the substitution for a defective address every block in a bank, in which a data read operation is being carried out, is independent of that in a bank, in which a data write or erase operation is being carried out.

[0163] However, in this preferred embodiment, the replacement of a block with a redundant block 403 is carried out only within a bank, to which the redundant block belongs.

[0164] (Fourth Preferred Embodiment)

[0165] FIG. 7 shows a preferred embodiment as a modification of the third preferred embodiment. The difference between this preferred embodiment and the preferred embodiment shown in FIG. 5 is that each of the banks BANK 0 and BANK 1 is provided with core decoders 420 a and 420 b for selecting a core in the bank, so as to correspond to two systems of address bus lines 305 a and 305 b. The “core” is herein a set of a plurality of blocks, each of which is the minimum unit for data erase. For example, eight blocks constitute one core. The bank comprises one core or a plurality of cores.

[0166] The core decoders 420 a and 420 b are supplied to the pre-decoder 402 on the side of the memory cell array 401 and to the pre-decoder 404 on the side of the redundant block 403 via core switching circuits 421 a and 421 b which are selectively on-off controlled by the busy register 315 . That is, in the bank wherein the output of the busy register 315 has “H”, the core address of the address bus line 305 b is decoded by the core decoder 420 b to be supplied to the pre-decoders 402 and 404 via the core switching circuit 421 b. The fact that the pre-decoders 402 and 404 are selectively active and inactive by the hit signal HITb is the same as that in the preceding third preferred embodiment. In the bank wherein the output of the busy register 315 has “L”, the core address of the address bus line 305 a is decoded by the core decoder 420 a to be supplied to the pre-decoders 402 and 404 via the core switching circuit 421 a. Also in this case, the pre-decoders 402 and 404 are selectively active and inactive in accordance with the hit signal HITa which is the result of the coincidence detection with the defective address.

[0167] Also according to this fourth preferred embodiment similar to the third preferred embodiment, the control of the substitution for a defective address every block in a bank, in which a data read operation is being carried out, is independent of that in a bank, in which a data write or erase operation is being carried out. In addition, in this preferred embodiment, the core decoders 420 a and 420 b for decoding core addresses are provided upstream of the pre-decoder 404 , so that the number of switches of the address line switching circuits 318 a and 318 b can be less than that in the preceding third preferred embodiment.

[0168] FIG. 10 is a conceptual diagram showing the state of the defective block substitution in the third or fourth preferred embodiment of an RWW type EEPROM. While the description of the relationship between power supplies has been omitted above, separate power supply lines 432 a and 432 b, which are connected to a reading power supply 431 a and a writing or erasing power supply 431 b, respectively, are provided commonly for the banks BANK 0 and BANK 1 as shown in this figure in order to meet the RWW specification. In accordance with the operation mode of each of the banks, these power supply lines 432 a and 432 b are selected by power supply line switching circuits 433 and 434 to be connected to each of the banks BANK 0 and BANK 1 .

[0169] FIG. 10 also shows the case where one bank BANK 0 has a large capacity and comprises a plurality of cores 0 through n, and the other bank BANK 1 comprises a single core. Eight blocks BLK 0 through BLK 7 are prepared for each block as normal blocks, and each core is provided with a spare block RBLK having a common core address. This spare block RBLK constitutes the above described redundant block 403 .

[0170] In the third and fourth preferred embodiments, for example, as shown in FIG. 10 , if the block BLK 7 of core 1 in the bank BANK 0 , is defective as marked X, the defective block is replaced with the spare block PBLK attached to core 1 . That is, in the third and fourth preferred embodiments, the block substitution range is not only limited to the same bank, but it is also limited to the same core. In other words, if a defect exists in a certain core, it is only possible to replace with a spare block having a core address common to that of the core.

[0171] (Fifth Preferred Embodiment)

[0172] FIG. 8 is a preferred embodiment wherein the preferred embodiment shown in FIG. 7 is modified to increase the degree of freedom for the block substitution. In this preferred embodiment unlike the preferred embodiment shown in FIG. 7 , hit signals HITa and HITb enter core decoders 420 a and 420 b. However, in this case, the hit signals HITa and HITb include a core address of a core including a spare block to be substituted, as well as an address coincidence detection signal.

[0173] Specifically, the defective address storing circuit 312 shown in FIG. 6 has stored therein the core address of the spare block to be substituted for the block of the defective block address, as well as the defective block address. The address comparator circuits 313 a and 313 b output the hit signals HITa and HITb including a core address, to which the spare block to be substituted belongs, mile outputting the coincidence detection signal of the defective address, to feed these signals to the core decoders 420 a and 420 b. Thus, the core decoder 420 a and 420 b decode the core address, which is assigned when the defective address is detected, to select the spare block.

[0174] FIG. 11 shows the state of the block substitution in this preferred embodiment, which corresponds to FIG. 10 . For example, as shown in this figure, if the block BLK 7 of core 1 is defective, the defective block BLK 7 can not only be replaced with the spare block RBLK belonging to core 1 , but it can also be replaced with the spare block RBLK of core 0 .

[0175] Therefore, according to this preferred embodiment, the degree of freedom for the defective block substitution can be further increased to realize a high relief efficiency.

[0176] (Sixth Preferred Embodiment)

[0177] FIG. 9 shows a preferred embodiment wherein the restrictions on the block substitution, which should be carried out within the limits of the bank, are removed to further enhance the degree of freedom for the block substitution. In this preferred embodiment unlike the preceding third through fifth preferred embodiments, a redundant block 403 is provided independently of the memory cell arrays 401 of the banks BANK 0 and BANK 1 . Specifically, the fact that the redundant block 403 is independent of the banks BANK 0 and BANK 1 means that an address is supplied only when a defective address is detected independently of the decoding circuits of the memory cell arrays 401 of the banks BANK 0 and BANK 1 .

[0178] That is, in addition to the address line switching circuits 318 a and 318 b of each of the banks BANK 0 and BANK 1 , the redundant block 403 is also provided with address line switching circuits 501 a and 501 b for switching two systems of address lines 305 a and 305 b. In addition, each of the banks BANK 0 and BANK 1 is provided with core decoders 420 a and 420 b which correspond to the two systems of address bus lines 305 a and 305 b, respectively, and the redundant block 403 is also provided with core dears 502 a and 502 b which correspond to the address bus lines 305 a and 305 b, respectively.

[0179] Hit signals HITa and HITb obtained in output signal lines 411 a and 411 b of two systems of address comparator circuits 313 a and 313 b are inverted to enter, as activated signals, the core decoders 420 a and 420 b of each of the banks BANK 0 and BANK 1 . In addition, the hit signals HITa and HITb obtained in the output signal lines 411 a and 411 b directly enter, as activated signals, the core decoders 502 a and 502 b on the side of the redundant block 403 .

[0180] Then, one address line switching circuit 501 a is turned on by the output of the core decoder 502 a, and the other address line switching circuit 501 b is turned on by the output of the core decoder 502 b. In addition, the defective address storing circuit 312 stores therein an address of a spare block to be substituted, as well as a defective block, and outputs the address of the spare block while outputting a coincidence detection signal. The disjunction of the outputs of the core decoders 502 a and 502 b is derived by an OR gate G to be used as a core selecting signal to control the activity and inactivity of the pre-decoder 404 on the side of the redundant block 403 .

[0181] In this preferred embodiment, if no defective block address is detected, the core decoders 420 a and 420 b of each of the banks BANK 0 and BANK 1 are active, and an access corresponding to the operation mode with resect to each of the banks BANK 0 and BANK 1 is obtained in accordance with the output of the busy register 315 . If a defective block address is detected, the core decoders 420