DETAILED DESCRIPTION OF THE INVENTION

[0020] The present invention will now be described more fully with reference to the accompanying drawings, in which a preferred embodiment of the invention is shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiment set forth herein. Rather, the embodiment is provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. It is also noted that like reference numerals may be used to designate identical or corresponding parts throughout the drawings.

[0021] FIG. 1 is a layout of a semiconductor memory device to be fabricated in accordance with one embodiment of the present invention using a capacitor formation method by electroplating. As shown in FIG. 1 , active regions A are defined by an isolation layer, and two word lines W/Ls overlap the active regions A. Bit lines B/Ls are arranged perpendicular to the word lines W/Ls at a different level or elevation. A bit line contact I is formed in the drain region of an active region A, and lower electrode contacts II are formed in the source region of the active region A. A capacitor lower electrode C of the semiconductor memory device is formed over each of the lower electrode contacts II.

[0022] FIGS. 2 through 8 are cross-sectional views taken along line B-B′ of FIG. 1 , illustrating a method for forming a capacitor of the semiconductor memory device. Although the present embodiment is described with reference to a capacitor over bit-line (COB) structure, as shown in FIGS. 2 through 8 , it is appreciated that the present invention is applicable to a capacitor under bit-line (CUB) structure.

[0023] Referring to FIG. 2 , an etch stop layer 30 is formed over a semiconductor substrate 20 on which one or more lower electrode pads 24 , one or more bit lines 26 and an interlayer dielectric (ILD) film 28 have been formed. Here, the semiconductor substrate 20 may be formed of Si, GaAs or InP or other suitable material.

[0024] The lower electrode pad 24 to be connected to a lower electrode of the capacitor is formed immediately above an impurity region 22 adjacent the surface of the semiconductor substrate 20 . Those of skill in the art will understand that electrode pad 24 is optional, and may not be required. The lower electrode pad 24 is formed of metal silicide, metal nitride, doped polysilicon, or a multi-layer of these or other suitable layers. For example, the metal silicide layer may be a WSi _x , TiSi _x , MoSi _x , CoSi _x or TaSi _x layer, and the metal nitride layer may be a TiN, TaN, WN, TiSiN, TiAlN, TiBN, ZrSiN, ZrAlN, MoSiN, MoAlN, TaSiN or TaAlN layer.

[0025] The ILD film 28 , which electrically isolates adjacent lower electrode pads 24 , is formed with a thickness of approximately 300-700 nm, preferably with a thickness of approximately 400 nm. The ILD film 28 is formed of silicon oxide. The etch stop layer 30 , which acts as an etch barrier layer during etching of a insulating pattern, is formed with a thickness of approximately 3-30 nm, preferably with a thickness of approximately 5 nm. The etch stop layer 30 may be a single layer of SiN _x , SiON _x , TiON _x , AlO _x , AlN _x , TaO _x or ZrO _x , or a multi-layer of these or other suitable layers. In one preferred embodiment, the etch stop layer 30 is formed of silicon nitride by chemical vapor deposition (CVD).

[0026] Next, an insulating layer 32 is formed over the etch stop layer 30 . The thickness of the insulating layer 32 is varied according to the dimension of the capacitor's lower electrode. In the present embodiment, the insulating layer 32 is formed with a thickness of approximately 400-1500 nm, and preferably with a thickness of approximately 600 nm. The insulating layer 32 may be a single layer of boro-phospho-silicate glass (BPSG), spin-on glass (SOG), phospho-silicate glass (PSG), SiO _x , SiN _x , SiON _x , TiO _x , AlO _x or AlN _x , or a multi-layer of these or other suitable layers.

[0027] The insulating layer 32 may be formed by sputtering, CVD, physical vapor deposition or atomic layer deposition. The method used to form the insulating layer 32 varies depending on the material selected for the insulating layer 32 . For example, if silicon oxide is selected as a material for the insulating layer 32 , it is preferable to apply a CVD technique in forming the insulating layer 32 .

[0028] Referring to FIG. 3, a photoetching process is applied to the resultant structure of FIG. 2 . In particular, the insulating layer 32 , the etch stop layer 30 and the ILD film 28 , which are formed generally above the lower electrode pad 24 , are selectively patterned by a reactive ion etching (RIE) method, thereby forming a insulating pattern 32 a , and an etch stop pattern 30 a , an ILD pattern 28 a , which collectively define a hole H through which the lower electrode pad 24 is exposed. The sidewalls of the insulating pattern 32 a and the ILD pattern 28 a are also exposed by the hole H, as illustrated. If the lower electrode pad 24 is omitted, the semiconductor substrate 20 is exposed through the hole H. The hole H corresponds to a portion of the lower electrode contact II to be formed as shown in FIG. 1 . The hole H is used for to form a plug and a lower electrode, which will be described later.

[0029] As shown in FIG. 3 , one or more holes H for forming the lower electrodes and the plugs are simultaneously formed. When a spacer of the bit line 26 which corresponds to a portion of the ILD pattern 28 a in contact with the sidewalls of the bit line 26 , and a capping layer of the bit line 26 which corresponds to a portion of the ILD pattern 28 a formed on the bit line 26 are formed of a material different from that used for the insulating pattern 32 a , the holes H may be formed in a self-aligning manner.

[0030] Referring to FIG. 4, a seed layer 34 for use in forming a lower electrode is formed on the bottom and sidewalls of the hole H and on the top of the insulating pattern 32 a with a thickness of approximately 5-30 nm, and preferably with a thickness of approximately 20 nm. In other words, the seed layer 34 is formed over the top of the lower electrode pad 24 , the surrounding sidewalls of the hole H and the top of the insulating pattern 32 a . It will be appreciated that where a given lower electrode pad 24 is omitted, the seed layer 34 would be formed on the top of the semiconductor substrate 20 exposed through the hole H, rather than on the top of the lower electrode pad 24 .

[0031] The seed layer 34 can be formed of any conductive material suitable for realizing the present invention. For example, the seed layer 34 can be a Pt group metal layer, a Pt group metal oxide layer, a conductive material layer with perovskite structure, a conductive metal layer, a metal silicide layer, a metal nitride layer, or a multi-layer of these or other suitable layers. For example, the Pt group metal layer may be a Pt, rhodium (Rh), iridium (Ir), osmium (Os) or palladium (Pd) layer, and the Pt group metal oxide layer may be a PtO _x , RhO _x , RuO _x , IrO _x or OsO _x , PdO _x layer. The conductive material layer with perovskite structure may be a CaRuO ₃ , SrRuO ₃ , BaRuO ₃ , BaSrRuO ₃ , CaIrO ₃ , SrIrO ₃ , BaIrO ₃ or (La,Sr)CoO ₃ layer, and the conductive metal layer may be a copper (Cu), aluminum (Al), tantalum (Ta), molybdenum (Mo), tungsten (W), gold (Au) or silver (Ag) layer. The metal silicide layer may be a WSi _x , TiSi _x , CoSi _x , MoSi _x or TaSi _x layer, and the metal nitride layer may be a TiN, TaN, WN, TiSiN, TiAlN, TiBN, ZrSiN, ZrAlN, MoSiN, MoAlN, TaSiN or TaAlN layer. Those of skill in the art will appreciate that lists are not exhaustive or exclusive and are not intended to limit in any way the scope of the invention as claimed.

[0032] In particular, the metal nitride layer can serve as an excellent diffusion barrier layer capable of preventing diffusion of silicon and metal, and can improve adhesion to metal layer. Thus, for example, if the seed layer 34 is formed of a multi-layer with a metal nitride layer, such as a TiN layer, and a Pt group metal layer formed on the metal nitride layer, such as a Ru layer, the adhesion of the seed layer 34 to the insulating pattern 32 a and the ILD pattern 28 a can be enhanced.

[0033] The seed layer 34 is preferably formed by a CVD method or a long-through-sputter (LTS) method, which is known to provide excellent step coverage. For example, if a Pt layer is selected as a material for the seed layer 34 , it is preferable to use the CVD or LTS method in forming the seed layer 34 . Alternatively, if a Ru layer is selected as a material for the seed layer 34 , it is preferable to apply the CVD method in forming the seed layer 34 . In this case, in forming the seed layer 34 of a Ru layer by the CVD method, bis(ethylcyclopentadienyl) ruthenium (Ru(E _t C _p ) ₂ ) may be used as a source gas and the flow rate of O ₂ gas may be adjusted to preferably approximately 200 seem, and the temperature of a wafer preferably may be in the range of approximately 300-400° C.

[0034] Referring to FIG. 5, a plating mask layer 36 is selectively deposited on the seed layer 34 formed on the top of the insulating pattern 32 a and along the edges of the seed layer 34 down to a predetermined depth, such that a predetermined lower extent of the seed layer 34 formed on the surrounding sidewalls of the hole H remain exposed, as illustrated. The plating mask layer 36 preferably has a thickness of approximately 1-30 um. The plating mask layer 36 acts as an insulating layer, so that deposition of a metal layer over the plating mask layer 26 is prevented during electroplating. The plating mask layer 36 , which is selectively formed on a portion of the seed layer 34 may be a single layer of SiO _x , SiN _x , SiON _x , TiO _x , AlO _x , AlN _x , TaO _x , ZrO _x , or other suitable layers, or a multi-layer of these layers or other suitable layers. Those skilled in the art will appreciate that the predetermined depth preferably is less than the predetermined lower extant of the seed layer 34 , leaving sufficient exposed sidewall within holes H for electroplating.

[0035] The plating mask layer 36 may be formed of silicon oxide or silicon nitride by PVD, for example, by a reactive sputtering method, or of SiO _x , SiN _x , SiON _x , TiO _x , AlO _x , AlN _x , ZrO _x or other suitable material by a plasma CVD or other suitable method. Due to poor step coverage of the PVD process, when PVD is used to deposit the plating mask layer 36 along the hole H, which is small, with a high aspect ratio as in illustrated embodiment of the present invention, the plating mask layer 36 can be deposited on the surface and only an upper sidewall portion, rather than through the entire sidewalls, of the seed layer 34 formed over the insulating pattern 32 a. When a plasma CVD process is used to form the plating mask layer 36 , the plating mask layer 36 can be deposited on the same portions of the seed layer 34 , for the same reason as in use of the PVD process.

[0036] Referring to FIG. 6, a conductive layer 38 is formed in the hole H by electroplating. In particular, the cathode of a power source 40 is connected via a first wire 42 to the seed layer 34 , while the anode of the power source 40 is connected via a second wire 44 to a source electrode 46 . In this state, the semiconductor substrate 20 is dipped in a plating solution for electroplating. Further description of the plating solution is described below. Then, on the exposed surface of the seed layer 34 in the hole H, a metal that is substantially the same as the metal of the source electrode 46 is deposited, thereby forming the conductive layer 38 in the hole H. Here, the conductive layer 38 is selectively deposited on substantially only the exposed seed layer 34 in the hole H, not on the plating mask layer 36 .

[0037] Furthermore, since the plating mask layer 36 is selectively formed on the surface of the seed layer 34 which overlies the insulating pattern 32 a and along the sidewalls of the seed layer 34 down to a predetermined depth, localized deposition of excess conductive material at the edges of the insulating pattern 32 a is prevented, so that no void occurs in the hole H. In other words, by use of an electroplating technique in forming the conductive layer 38 in the hole H, voids in the hole, which are caused with the conventional CVD and PVD methods, are avoided.

[0038] The conductive layer 38 may be a single layer of Pt, fr, Ru, Rh, Os, Pd, Cu, Ag, Au, Ni, Co, or other suitable material, or a multi-layer of these materials. For example, when Pt is selected as a material for the conductive layer 38 , it is preferable that an ammonium platinum nitride (Pt(NH ₃ ) ₂ (NO ₂ ) ₂ ) solution is used as a plating solution, and a Pt electrode is selected as the source electrode 46 . In this case, the temperature of a plating bath may be set in the range of approximately 0-95° C., preferably at 80° C., the concentration of the ammonium platinum nitride (Pt(NH ₃ ) ₂ (NO ₂ ) ₂ ) plating solution may be in the rage of approximately 1 to 20 g/l, preferably at approximately 10 g/l, pH of the plating solution may be in the range of approximately 0.5-9.0, preferably at approximately 1.0, the concentration of a conductive sulfuric acid in the plating solution may be in the range of approximately 0.5-1.5 g/l, the current density may be in the range of approximately 0.2-3 A/cm ² , but preferably at approximately 1 (A/cm ² ) and the plating time may be in the range of approximately 50-800 seconds, preferably approximately 150 seconds.

[0039] When the conductive layer 38 preferably is formed of Pt, an ammonium chloroplatinate ((NH ₄ ) ₂ PtCl ₆ ) or chloroplatinic acid (H ₂ PtCl ₆ ) solution can be used as the electroplating solution.

[0040] It is appreciate that instead of Pt, other metal salts can be incorporated into the electroplating solution. For this case, the hole H can be filled with the metal corresponding to the metal salt of the electroplating solution. The electroplating solution may contain a Pt, Ir, Ru, Rh, Os, Pd, Cu, Ag, Au, Ni or Co salt, or a composite salt of these or other suitable metal salts. For example, as the plating solution, (NH ₄ ) ₂ PtCl ₆ , H ₂ PtCl ₆ , RuNOCl ₃ , RuCl ₃ , IrCl ₄ or (NH ₄ ) ₂ IrCl ₆ can be used. The source electrode 46 preferably is formed of Pt, Ir, Ru, Rh, Os, Pd, Cu, Ag, Au, Ni or Co, or an alloy of these or other suitable metals.

[0041] Referring to FIG. 7 , the plating mask layer 36 and a portion of the seed layer 34 and the conductive layer 38 are removed by a predetermined thickness of approximately 50-200 nm, and preferably approximately 100 nm through dry etching or CMP, so that a seed pattern 34 a and patterned conductive layers 38 a and 38 b are separated by a unit cell. The insulating pattern 32 a of FIG. 6 is removed in a hydrofluoric acid (HF) solution by wet etching. When the insulating pattern 32 a is etched by the wet etching, the seed pattern 34 a is not removed, and the ILD pattern 28 a is protected from etching by the etch stop pattern 30 a . As a result, the patterned conductive layer 38 a , which is hereinafter termed a plug, and the patterned conductive layer 38 b , which is hereinafter termed a lower electrode of a capacitor, are formed, respectively, at the lower and upper locations of the hole H divided by dashed lines, as shown in FIG. 7 . The plug 38 a may be as high as approximately 200-800 nm. The lower electrode 38 b on which a dielectric layer is to be formed by a subsequent process has a height of approximately 400-1500 nm. The width of the lower electrode 38 b is determined by the size of the hole H, but typically is approximately 300 nm or less for ultra large-scale integrated semiconductor memory device. In FIG. 7 , the seed pattern 34 a is incorporated into the lower electrode 38 b , but need not be incorporated into the same if necessary. The seed pattern 34 a can be removed after the etching of the insulating pattern 32 a.

[0042] Referring to FIG. 8, a capacitor dielectric layer 48 is deposited, over the resultant structure of FIG. 7 having the lower electrode 38 b , to a thickness of approximately 10-50 nm, and preferably to a thickness of approximately 30 nm. The dielectric layer 48 preferably is a Ta ₂ O ₅ , SiTiO ₃ (STO), (Ba,Sr)TiO ₃ (BST), PbZrTiO ₃ , SrBi ₂ Ta ₂ O ₅ (SBT), (Pb,La)(Zr,Ti)O ₃ or Bi ₄ Ti ₃ O ₁₂ layer, or a multi-layer of these or other suitable layers.

[0043] An upper electrode 50 is formed over the dielectric layer 48 with a thickness of approximately 30-150 nm, preferably and approximately 50 nm, by a sputtering or CVD method. The upper electrode 50 preferably comprises a material layer of substantially the same material as the material of the seed layer 34 for the lower electrode 38 b.

[0044] Alternatively, the upper electrode 50 may comprises a Pt group metal layer, for example, a Pt layer, with application of a metal-organic deposition (MOD) method. In this case, if a spin coating technique is used to deposit the upper electrode 50 with a MOD solution, which typically is a mixture of 10% Pt-acetylacetonate and 90% ethanol, the thickness and the density of the Pt layer to become the upper electrode 50 can be controlled by varying the spin rate and the concentration of the Pt-MOD solution.

[0045] In addition, when the upper electrode 50 is formed of a Pt layer, a spin coating technique can be applied with a colloidal solution. In this case, a Pt colloidal solution with approximately 5% solid content by weight may be prepared by uniformly dispersing Pt colloidal particles having an average size of approximately 30-50 Å in an organic solvent such as alcohol. Then, the Pt colloidal solution may be spin coated to a thickness of approximately 1000 Å, and subjected to an annealing process at a temperature of approximately 300-500° C. for approximately 10 minutes to evaporate the alcoholic component from the deposited layer, so that the formation of upper electrode 50 of Pt layer is complete.

[0046] As previously mentioned, in the formation of a capacitor of a semiconductor device according to the present invention, a seed layer for electroplating is formed on the sidewalls of a hole that exposes the lower electrode pad, and on the surface of a insulating pattern. A plating mask layer is selectively deposited on the seed layer formed over the insulating pattern and in the sidewalls of the hole to a predetermined depth from the upper edges of the insulating pattern, such that a portion of the seed layer in the hole H is exposed. As a result, a patterned conductive layer for use as a lower electrode can be selectively deposited only in a hole typically having a high aspect ratio, without occurrence of voids in the hole. Therefore, a lower electrode conductive pattern having a width of approximately 300 nm or less for a highly-integrated semiconductor memory device can be obtained by the inventive electroplating method.

[0047] While this invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made thereto without departing from the spirit and scope of the invention as defined by the appended claims.