DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0029] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention must not be interpreted as being restricted to the embodiments. The embodiments are provided to more completely explain the present invention to those skilled in the art. In the drawings, the thicknesses of layers or regions are exaggerated for clarity. Like reference numerals in the drawings denote the same members. Also, when it is written that a layer (film) is formed “on” another layer (film) or a substrate, the layer (film) can be formed directly on the other layer (film) or the substrate, or other layers (films) can intervene therebetween.

[0030] FIG. 1 conceptually shows the structure of electrodes and a dielectric film according to an embodiment of the present invention. A capacitor according to the present invention shown in FIG. 1 is a planar type capacitor. However, the capacitor according to the present invention can have a variety of shapes such as a cylindrical shape, a fin shape or a shape in which the longitudinal cross-section of the capacitor is a trapezoid or an inverted-trapezoid.

[0031] Referring to FIG. 1, a lower electrode 10 in a capacitor according to the embodiment of the present invention is formed of a refractory metal such as Ti, Ta and W or a refractory metal compound such as TiN, TiSiN, TiAlN, TaN, TaSiN, TaAlN and WN. In particular, when the lower electrode 10 has a three-dimensional structure such as a cylindrical shape, a refractory metal or refractory metal compound deposited by CVD or ALD providing good step coverage is preferable. The CVD or ALD method for the refractory metal or its compound has already been developed, so it can be readily employed. The formation of the lower electrode 10 by CVD or ALD will be described in detail below.

[0032] A dielectric film 12 of a capacitor according to this embodiment is formed of a high dielectric material having a significantly-higher dielectric constant than a silicon oxide film or a nitride film used in the prior art. Examples include Ta ₂ O ₅ , Al ₂ O ₃ and TaON. It is preferable that the dielectric film 12 is also deposited by CVD or ALD, which may have been utilized likewise for the lower electrode 10 , since the CVD or ALD provides suitable step coverage. The formation of the dielectric film 12 by CVD or ALD will also be described in detail below.

[0033] An upper electrode 14 of the capacitor is formed of a platinum-family metal such as Ru, Pt or Ir or a platinum-family metal oxide such as RuO ₂ , PtO or IrO ₂ . Such materials provide good electrical characteristics such as the leakage current characteristics, in capacitors that employ a high dielectric material as a dielectric film. It is preferable that the dielectric film 14 is also deposited by CVD or ALD likewise for the dielectric film 12 and the lower electrode 10 to obtain good step coverage. The formation of the upper electrode 14 by CVD or ALD will also be described in detail below.

[0034] As shown in FIG. 2 , in a capacitor according to a modified embodiment of the present invention, a reaction preventing film 20 can be further provided between the lower electrode 10 formed of a refractory metal or its compound and the dielectric film 12 formed of a high dielectric material, in order to prevent a reaction between the material of the lower electrode 10 and the material of the dielectric film 12 . Preferably, the reaction preventing film 20 is formed of Si ₃ N ₄ , Al ₂ O ₃ , TaON, HfO ₂ or ZrO ₂ . As will be described below, preferably, the reaction preventing film 20 is deposited in an amorphous state, and then crystalized while thermally treating the dielectric film 12 after the upper electrode 14 is deposited.

[0035] FIG. 3 is a graph showing the leakage current densities of planar capacitors shown in FIGS. 1 and 2 . In the measurements shown in FIG. 3 , the lower electrode of the capacitor is CVD-TiN, and the dielectric film is a Ta ₂ O ₅ . The Ta ₂ O ₅ dielectric film is formed in two steps by primarily depositing 90 Å of Ta ₂ O ₅ and annealing the Ta ₂ O ₅ using UV-O ₃ , and secondly depositing 60 Å of Ta ₂ O ₅ and annealing the Ta ₂ O ₅ using UV-O ₃ . In FIG. 3 , ▾ and  indicate capacitors according to the present invention in which an upper electrode is made of CVD-Ru. In particular, in the capacitor designated by , an Si ₃ N ₄ reaction preventing film is interposed between a CVD-TiN lower electrode and a Ta ₂ O ₅ dielectric film. □ designates a conventional capacitor in which the upper electrode is made of CVD-TiN, and ◯ designates a conventional capacitor in which the upper electrode is made of physical vapor deposition (PVD)-TiN.

[0036] As can be seen from FIG. 3 , the resulting leakage current densities of the capacitors (▾ and ) according to the present invention using a CVD-Ru upper electrode are better than or equal to those of the conventional capacitors (□ and ◯) using a TiN upper electrode. In particular, considering that the operating voltage of a capacitor is generally on the order of ±1 V, it becomes evident that the capacitors according to the present invention guarantee appropriate leakage current densities.

[0037] As for the conventional capacitors using a TiN upper electrode, the leakage current density of the CVD-TiN/Ta ₂ O ₅ /CVD-TiN capacitor (□) is inferior to that of the PVD-TiN/Ta ₂ O ₅ /CVD-TiN capacitor (◯). This is because CVD-TiN is deposited at a high temperature (about 500° C. or more) under a reducing atmosphere where oxygen within a Ta ₂ O ₅ dielectric film is affected, such as, TiCI ₄ or NH ₃ atmosphere, whereas PVD-TiN is deposited at a low temperature (about 400° C. or less) under non-reducing atmosphere. Though described later, likewise, the CVD-Ru upper electrode in each of the capacitors (▾ and ) is deposited using an O ₂ gas which provides a non-reducing atmosphere and can cure the oxygen vacancy of a Ta ₂ O ₅ dielectric film at a relatively low temperature, thus providing excellent leakage current characteristics. However, the PVD-TiN upper electrode is inadequate for cylindrical capacitors having a threedimensional-shaped dielectric film having a large step difference.

[0038] As described above, the present invention provides an MIM capacitor using a dielectric film made of a high dielectric material, which provides an excellent step coverage and an excellent leakage current characteristic and also satisfies the economic efficiency and the suitability for mass production by forming the lower electrode 10 of a refractory metal or a conductive compound containing the refractory metal, and forming the upper electrode 14 of a platinum-family metal or a platinum-family metal oxide, as compared to conventional capacitors in which the upper and lower electrodes are formed of the same material.

[0039] Methods of manufacturing capacitors according to embodiments of the present invention will now be described with reference to FIGS. 4 through 9 . Hereinafter, methods of manufacturing a capacitor according to the embodiment of the present invention will be described using a capacitor having a cylindrical electrode structure in which a CVD-Ru upper electrode is formed on a Ta ₂ O ₅ dielectric film which is formed on a CVD-TiN lower electrode. However, the present invention is not limited to this embodiment, and it is apparent that the present invention can be embodied in various forms by using the above-described various materials.

[0040] Referring to FIG. 4, a lower electrode contact plug 110 is formed in an interlayer dielectric film 100 below which a device (not shown) such as a transistor is formed, and insulating films 120 and 140 as mold layers for forming a cylindrical lower electrode are provided on the resultant structure. For example, the insulating films 120 and 140 may comprise silicon oxide. In FIG. 4 , reference numeral 130 , which acts as an etch stop layer while the insulating film 140 is being etched, can be formed of a material having an etch selectivity with respect to the insulating film 140 , for example, silicon nitride. The total thickness of the insulating films 120 , 130 and 140 corresponds to the height of a lower electrode. In FIG. 4 , the etch stop layer 130 is sandwiched between the insulating films 120 and 140 . However, the location of the etch stop layer 130 is not limited to this embodiment. For example, the etch stop layer 130 can be formed on the interlayer dielectric film 100 , exposing the lower electrode contact plug 110 .

[0041] Next, as shown in FIG. 5, a trench 150 , exposing the lower electrode contact plug 110 , is formed by etching the insulating films 140 and 120 and the etch stop layer 130 . A lower electrode will be formed on the side walls and bottom surface of the trench 150 .

[0042] Then, as shown in FIG. 6, a TiN layer 160 for a lower electrode is conformally deposited on the entire surface of the trench 150 by CVD or ALD, and a material having excellent fluidity, for example, silicon oxide, is deposited on the TiN layer 160 .

[0043] The TiN layer 160 is formed by CVD at a pressure of 0.1 to 10 Torr and at 600 to 700° C. using TiCl ₄ and NH ₃ as a source gas. When the TiN layer 160 is deposited by ALD, the same source gases are used, but only one source gas (for example, TiCl ₄ ) at one time is supplied and chemically adsorbed on a substrate. Then, non-adsorbed source gas within a reaction chamber is purged, and the other source gas (for example, NH ₃ ) is supplied. In this way, the formation of the TiN layer 160 on the substrate is repeated. When the TiN layer 160 is formed by ALD, the deposition is performed at a temperature of 450 to 550° C.

[0044] Thereafter, the structure of FIG. 6 is etched by chemical mechanical polishing or etch-back to expose the insulating film 142 , thereby isolating adjacent lower electrodes from each other. The exposed insulating film 142 and an insulating film 170 , which fills the trench, are removed, resulting in a structure shown in FIG. 7 . If the insulating films 142 and 170 are made of the same material, they can be removed together in a single wet-etching or dry-etching process.

[0045] As shown in FIG. 8, a Ta ₂ O ₅ dielectric film 180 and a Ru upper electrode 190 are formed on the cylindrical TiN lower electrode 162 , thereby completing the formation of a capacitor.

[0046] To be more specific, the Ta ₂ O ₅ dielectric film 180 is formed by CVD at 400 to 500° C. or by ALD at about 300° C. during supply of a Ta source gas obtained by vaporizing liquid Ta(OC ₂ H ₅ ) ₅ using a vaporizer, and an O ₂ gas. As described above, the Ta ₂ O ₅ dielectric film 180 is preferably deposited at a low temperature, thus providing excellent step coverage.

[0047] The electrical characteristics of the Ta ₂ O ₅ dielectric film 180 can be improved by an ultraviolet thermal treatment or plasma process at an oxygen or nitrogen atmosphere containing O ₃ , after it is deposited. Also, the Ta ₂ O ₅ dielectric film 180 can be deposited in multiple steps by repetitive deposition and UV-O ₃ thermal treatment. Here, a dielectric film can be formed of a composite film by depositing and thermally treating different dielectric materials. Also, the dielectric constant of the Ta ₂ O ₅ dielectric film 180 can be increased by thermal treatment for crystallization at or above about 700° C.

[0048] Here, it is preferable that the thermal treatment for crystallization of the Ta ₂ O ₅ dielectric film 180 is performed after the upper electrode is formed, as will be described later.

[0049] The Ru upper electrode 190 is formed by CVD or ALD at 250 to 450° C. while an Ru source gas obtained by vaporizing liquid Ru(C ₂ H ₅ C ₅ H ₄ ) ₂ and an O ₂ reaction gas are being supplied. The surface morphology and electrical characteristics of the Ru film vary according to the conditions for deposition. As disclosed in Korean Patent Application No. 99-61337 filed on Dec. 23, 1999 by the present applicant and incorporated herein by reference, the Ru upper electrode 190 having a desired property can be obtained by varying the deposition conditions over the early and late stages of deposition. In this case, to be more specific, at the early stage of deposition, ruthenium deposited for a time period ranging from 5 seconds to 5 minutes in a state where the pressure within the reaction chamber is maintained at 10 to 50 Torr, more preferably, at 20 to 40 Torr, and the flow of an O ₂ gas is maintained at 500 to 2000 sccm, more preferably, at 1000 to 1500 sccm. At the late stage of deposition, ruthenium is deposited until an Ru film having a desired thickness is formed, by maintaining the pressure within a reaction chamber at 0.05 to 10 Torr, more preferably, at 0.1 to 3 Torr, and maintaining the flow of an O ₂ gas at 10 to 300 sccm, more preferably, at 50 to 150 sccm.

[0050] In the modified embodiment of the present invention, as shown in FIG. 9, a Si ₃ N ₄ reaction prevention film 200 can be sandwiched between the lower electrode 162 and the dielectric film 180 . In this embodiment, the silicon nitride film 200 is formed on the entire surface of the substrate of FIG. 7 on which the cylindrical TiN lower electrode 162 is formed, by CVD using a Si source gas such as a silane-family gas and an N source gas such as NH ₃ . Next, the dielectric film 180 and the upper electrode 190 are formed on the resultant structure, thereby forming a capacitor according to this embodiment of the present invention. Here, preferably, the Si ₃ N ₄ reaction prevention film 200 is deposited to be in an amorphous state at 600 to 700° C., and the dielectric film 180 is thermally treated and crystallized after the upper electrode 190 is formed. If the crystallization of the Ta ₂ O ₅ dielectric film 180 is performed before the Ru upper electrode 190 is formed, the Si ₃ N ₄ reaction prevention film 200 operates as a crystallization seed layer of the Ta ₂ O ₅ dielectric film 180 , so that the dielectric constant of the Ta ₂ O ₅ dielectric film 180 slightly increases. In contrast, when the crystallization of the Ta ₂ O ₅ dielectric film 180 is performed after the Ru upper electrode 190 is formed, the Ru upper electrode 190 operates as a crystallization seed layer of the Ta ₂ O ₅ dielectric film 180 , so that the dielectric constant of the Ta ₂ O ₅ dielectric film 180 increases substantially.

[0051] FIGS. 10 and 11 are graphs showing the accumulative distributions according to the electrical characteristics of a capacitor according to the embodiment of the present invention. In these experiments, a cylindrical capacitor having a CVD-Ru upper electrode/CVD-Ta ₂ O ₅ dielectric film/CVD-TiN lower electrode structure is used, the height of the lower electrode is set to be about 1 μm, and the thickness of the dielectric film is set to be about 150 Å.

[0052] Referring to FIG. 10 , the capacitance of a capacitor according to the embodiment of the present invention is about 40 fF per cell, and the ratio of C _min /C _max is about 0.99. Referring to FIG. 11 , when ±1 voltage was applied, a good leakage current density, about 10 ⁻¹⁶ A per cell, was measured.

[0053] In the above-described embodiments, upper and lower electrodes and a dielectric film are formed by depositing a particular material using a particular method. However, if a source gas is appropriately selected, other materials mentioned above can be used. In cases of capacitors not having a three-dimensional shape such as a cylindrical shape, it is apparent that the upper and lower electrodes and the dielectric film can be formed by other methods such as sputtering.

[0054] As described above, in capacitors using a high dielectric material to form a dielectric film, according to the present invention, a lower electrode is formed of a refractory metal or a conductive compound containing the refractory metal, the deposition and etching of which are put into practical use, so that a three-dimensional lower electrode can be formed with excellent step coverage. Also, an upper electrode is formed of a platinum-family metal or a platinum-family metal oxide, so that a capacitor having superior electrical characteristics can be obtained.

[0055] Also, an MIM capacitor according to the present invention satisfies the step coverage, the electrical characteristics and manufacturing costs, compared to a conventional MIM capacitor in which the upper and lower electrodes are formed of the same material such as a platinum-family metal, a refractory metal or a conductive compound including the refractory metal. In particular, by developing and applying a new CVD method to deposit a platinum-family metal such as Ru, which heretofore has had no practical deposition methods, the electrical characteristics of a capacitor can be guaranteed. Accordingly, the capacitors according to the present invention can be mass-produced.

[0056] While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made herein without departing from the spirit and scope of the invention as defined by the appended claims.