DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0035] FIG. 1 shows an illustrative embodiment of CDR signaling apparatus 10 in accordance with the invention. This apparatus includes CDR signal source 20 and receiver 40 . Although elements 20 and 40 could be on the same integrated circuit, that is generally not the case and they are more typically portions of separate integrated circuits or circuit assemblies. For example, in systems like those shown in FIG. 12 , receiver 40 could be part of element 500 / 600 , while source 20 could be part of any other element(s) 1004 , 1006 , 1008 , and/or 1010 .

[0036] CDR signal source 20 includes reference clock signal source 22 and CDR data signal source 30 , which can be conventional or substantially conventional. Reference clock signal source 22 produces a reference clock signal having a precise frequency relationship to the clock frequency embedded in the CDR data signal produced by CDR data signal source 30 . For example, reference clock signal source 22 can produce a reference clock signal having the same frequency as the clock frequency embedded in the CDR data signal or any convenient fraction or multiple of the embedded clock frequency. In particular, the reference clock signal frequency REFCLK is related to the embedded clock frequency EMBCLK by the following relationship:

REFCLK*W=EMBCLK,

[0037] where W is a convenient scale factor such as 0.5, 1, 2, 4, etc. The dotted line between elements 22 and 30 indicates that there is such a frequency relationship between the outputs of those elements, and indeed the reference clock signal produced by source 22 (or some frequency-divided or frequency-multiplied version of that signal) may be used by element 30 to establish the frequency of the CDR data signal. There does not, however, need to be any particular phase relationship between the output signals of elements 22 and 30 .

[0038] The output signal of reference clock signal source 22 is applied to conventional differential signaling driver 24 to produce a pair of differential REFCLK output signals on leads 26 a and 26 b . (This is optional. The reference clock signal could instead be transmitted between elements 20 and 40 as a single signal on a single lead if desired.)

[0039] As has been mentioned, CDR data signal source 30 can be a conventional source of a CDR data signal. That signal is applied to conventional differential signaling driver 32 to produce a pair of differential CDR data output signals on leads 34 a and 34 b . (Once again, differential signaling for the CDR data signal is optional, and the CDR data signal could instead be transmitted between elements 20 and 40 via a single lead.)

[0040] At receiver 40 the differential REFCLK signals on leads 26 a and 26 b are applied to conventional differential driver 42 in order to convert the received REFCLK signals back to a signal on a single lead for application to CDR circuitry 50 . Similarly, the differential CDR data signals on leads 34 a and 34 b are applied to conventional differential driver 44 in order to convert the received CDR data signals back to a signal on a single lead for application to CDR circuitry 50 .

[0041] CDR circuitry 50 uses the received REFCLK and CDR data signals to extract from the CDR data signal a clock signal and a data signal. These signals are applied to deserializer 60 , which converts the applied serial data to parallel data. The parallel data signals are applied to synchronizer 70 in synchronism with the clock signal produced by CDR circuitry 50 . Synchronizer 70 buffers the parallel dat for ultimate application to PLD core 80 in synchronism with another clock signal 82 supplied to synchronizer 70 by PLD core 80 .

[0042] FIG. 1A shows an alternative embodiment of CDR signaling apparatus 10 ′ in which the reference clock signal source 22 ′ used by receiver 40 is separate from CDR signal source 20 ′. CDR signal source 20 ′ may be basically the same as CDR signal source 20 in FIG. 1 except that it does not need elements like 24 for outputting the reference clock signal for conveyance to receiver 40 . Instead, a separate reference clock signal source 22 ′ supplies the reference clock signal to receiver 40 via leads 26 a ′ and 26 b ′. Reference clock signal source 22 ′ can be similar to reference clock signal source 22 in FIG. 1 , and everything said about source 22 in FIG. 1 is equally applicable to source 22 ′ in FIG. 1A (except, of course, that source 221 is separate from source 20 ′ and does not provide an input or clock reference to source 30 ). In addition it should be said that although there needs to be a precise, known, frequency relationship between sources 22 and 22 ′, the frequencies of those sources do not have to be the same (again, scale factors like 0.5, 1, 2, 4, etc., can exist between these frequencies), and no particular phase relationship is required between sources 22 and 22 ′. Receiver 40 in FIG. 1A can be the same as receiver 40 in FIG. 1 .

[0043] Configurations of the type shown in FIG. 1A can be used when source 20 ′ and receiver 40 are relatively far apart, possibly making it undesirable to have to run both CDR data leads 34 and reference clock leads 26 between widely spaced elements 20 ′ and 40 . In that event, source 22 ′ can be placed relatively close to receiver 40 so that only leads 34 need to be relatively long, while leads 26 ′ can be relatively short. As a specific illustration, elements 20 ′ and 40 may be on respective different continents, with source 22 ′ being located near receiver 40 so that only intercontinental links are needed for the CDR data signals 34 themselves. (In this connection it should be pointed out that just as any of links 34 , 26 , 26 ′ can alternatively be single signals, they can alternatively be transmitted (in whole or in part) by means other than wire leads. For example, they can be wholly or partly transmitted by radio, light, or in any other suitable and desired way. The same is true for the signals requiring transmission in other embodiments such as the ones shown in FIGS. 7 and 7 A.)

[0044] An illustrative embodiment of a portion 100 of CDR circuitry 50 is shown in more detail in FIG. 2 . Circuitry 100 is basically a phase locked loop (“PLL”) circuit and it will therefore sometimes be referred to as such herein. PLL 100 includes phase frequency detector (“PFD”) circuit 110 , which receives the REFCLK signal output by buffer 42 in FIG. 1 and the output signal of W prescaler circuit 140 . PFD 110 , which can be conventional, compares the phase and frequency of the two signals it receives and outputs a signal indicative of whether the output signal of prescaler 140 should be speeded up or slowed down to better match the phase and frequency of the REFCLK signal. Charge pump circuit 120 (which can also be conventional) integrates the output signal of PFD 110 and produces a VCO current control signal appropriate to controlling voltage controlled oscillator (“VCO”) 130 in the manner required to make the output signal of VCO 130 (after processing by W prescaler 140 ) better match the REFCLK signal with respect to phase and frequency. The output signal of VCO 130 is applied to W prescaler 140 , which divides the VCO output signal frequency by a scale factor W in order to produce one of the two signals applied to PFD 110 . Scale factor W is the same value used in the above-mentioned relationship between REFCLK and EMBCLK. W prescaler 140 is preferably programmable or otherwise controllable to operate using any of several values of W. For example, the desired value of W may be stored in one or more programmable function control elements (“FCEs”) which are part of receiver 40 .

[0045] From the description of PLL 100 provided thus far it will be seen that this circuit operates to cause VCO 130 to operate at a frequency which closely matches the EMBCLK frequency. VCO 130 outputs eight clock signals, all having the EMBCLK frequency but shifted in phase relative to one another so that they collectively divide the period of the EMBCLK signal into eight equal time intervals. VCO 130 may be programmable or otherwise controllable by the D signals to help it perform over a wide range of possible operating frequencies. For example, the D signals may control what may be referred to as a “coarse” adjustment of VCO 100 , while the VCO current control signal from charge pump 120 is responsible for a “fine” adjustment of the VCO. The desired value of D may be stored in one or more programmable FCEs which are part of receiver 40 .

[0046] The reset signal shown in FIG. 2 allows PLL 100 to be reset and released to start in a controlled manner. For example, it may be necessary or desirable to reset PLL 100 when a loss-of-lock condition is detected in PLL 100 . (This and other aspects of various reset operations are described in more detail later in this specification.) The reset signal resets charge pump 120 , VCO 130 , and W prescaler 140 . The W, D, and reset signals may all come from PLD core 80 ( FIG. 1 ).

[0047] The power down signal shown in FIG. 2 allows PLL 100 to be turned off if it is not going to be used. This can be done by having the power down signal turn off the current to VCO 130 . In the example of the VCO 130 construction shown in FIG. 3 and described in more detail below, this can be done by turning off current source 131 , thereby turning off the current to differential drivers 132 . The power down signal may come from an FCE associated with PLL 100 . Turning off PLL 100 in this way saves power if the PLL is not going to be used.

[0048] An illustrative construction of VCO 130 is shown in part in more detail in FIG. 3 . Differential drivers 132 a - d are interconnected in a closed loop series. The time required for a signal transition to make one complete circuit of this loop (via either the true or complement path) is half the period of the clock signal. The speed at which each driver 132 operates, and therefore the signal propagation speed of the loop, is determined (at least to some extent) by the amount of current supplied to the drivers from current source 131 . The D signals (mentioned above in connection with FIG. 2 ) can be used to programmably select any one of several possible current ranges within which current source 131 can operate. The D signals therefore control the above-mentioned “coarse” adjustment of current source 131 and hence VCO 130 . The VCO current control signal (from charge pump 120 in FIG. 2 ) provides additional dynamic control of the current supplied by current source 131 . In particular, the VCO current control signal adjusts the current supplied by current source 131 within whatever range has been selected by the D signals. Thus the VCO current control signal provides dynamic “fine” adjustment of current source 131 and hence VCO 130 . (The power down signal (also mentioned above in connection with FIG. 2 ) can be used to programmably turn off current source 131 in the event that PLL 100 is not going to be used at all.)

[0049] From the foregoing it will be seen that (within any of several possible frequency ranges selected using the D signals), the frequency of the clock signal can be increased or decreased by changing the VCO current control signal. The true and complement paths through the closed loop of drivers 132 are collectively tapped at eight points that effectively divide the clock signal period into eight equal time intervals. The signals at those eight points are output as the above-mentioned eight, equally phase-shifted, clock signals.

[0050] Although single-ended drivers could be used in VCO 130 in place of differential drivers 132 , differential drivers are preferably used for several reasons. One of these reasons is that differential drivers tend to be less susceptible to noise. Differential drivers can be more easily made to operate on smaller input signal swings (e.g., 300 millivolts instead of 3 volts). Differential drivers can also more easily be made faster, better able to resist jitter, and more immune to noise. Another reason that differential drivers are preferred for VCO 130 is that differential output signals are needed from the VCO. It will also be understood that voltage control of VCO 130 could be used in place of the above-described current control, but current control is presently preferred.

[0051] An illustrative embodiment of a further portion 150 of CDR circuitry 50 is shown in FIG. 4 . Unlike PLL 100 , which is typically at least predominantly analog circuitry, the circuitry 150 shown in FIG. 4 is preferably digital circuitry. Because it is both digital and operates like a phase locked loop, circuitry 150 is sometimes referred to herein as digital phase locked loop (“DPLL”) circuitry 150 .

[0052] DPLL 150 includes phase detector 160 , which receives both the CDR data signal (from driver 44 in FIG. 1 ) and the clock signals output by multiplexer 190 . As will be described more fully below, one of the two output signals of multiplexer 190 is intended for comparison with rising edges in the CDR data signal, while the other of the two output signals of multiplexer 190 is intended for comparison with falling edges in the CDR data signal. Phase detector 160 compares the phases of the signals it receives and produces UP output signal pulses if the clock signals need to be speeded up to better work with the phase of the transitions in the CDR data signal, or DOWN output signal pulses if the clock signals need to be slowed down to better work with the phase of the transitions in the CDR data signal. These UP and DOWN signal pulses are applied to phase interpolation state machine 162 .

[0053] Phase interpolation state machine 162 responds to each UP and DOWN signal pulse by changing state internally. However, state machine 162 does not produce output signal pulses in response to every UP or DOWN signal pulse it receives. Instead, state machine 162 outputs further UP or DOWN signal pulses only after a trend has emerged in the signals it receives. In other words, state machine 162 acts somewhat like a digital low-pass filter to prevent the rest of the FIG. 4 circuitry from responding too quickly to what may turn out to be only a short-term indication of phase mismatch produced by phase detector 160 . State machine 162 therefore builds some desirable latency into the circuitry shown in FIG. 4 . (The debug output signals of circuitry 162 are optional and can be used for monitoring circuit performance if desired.)

[0054] The UP and DOWN signal pulses that are output by state machine 162 are counted and decoded by up/down counter and decoder circuitry 164 . (The debug output signals of circuitry 164 are again optional and are for further monitoring circuit performance.) Some of the outputs of circuitry 164 are used by clock multiplexer circuitry 170 to select (1) the two of the eight clock input signals from PLL 100 that work best with rising edges in the CDR data signal, and (2) the two of the eight clock input signals from PLL 100 that work best with falling edges in the CDR data signal. It should be apparent from what has just been said that each of these pairs of selected clock signals includes signals that are immediately adjacent to one another in phase (among the eight phases available in the eight clock signals). It should also be apparent that each of the signals in each of these pairs will be 180° out of phase with a respective one of the signals in the other pair. Thus from eight input clock signals, circuitry 170 dynamically selects four output clock signals. For example, if the eight input clock signals are numbered 0 - 7 in phase order, circuitry 170 might during some period of time select clock signals 0 and 1 as best working with rising edges in the CDR data signal, and signals 4 and 5 as best working with falling edges in the CDR data signal. The four clock signals selected by circuitry 170 are applied to analog interpolator 180 and also to digital interpolator 182 . The user of the device can elect to use either of these two interpolators.

[0055] Analog interpolator 180 operates by dividing into eight equal sub-intervals the time interval between the two clock signals in each pair of clock signals that it receives from circuitry 170 . The output signals of circuitry 164 that analog interpolator 180 also receives control the interpolator to select one of these sub-intervals for each pair of clock signals and to produce a shifted clock signal synchronized with that sub-interval. The selected sub-interval (and thus the shifted clock signal) is the one that works best with the appropriate one of rising or falling edges in the CDR data signal. Thus the two shifted clock signals produced by analog interpolator 180 are respectively optimized (or very nearly optimized) to work with rising or falling edges in the CDR data signal. Multiplexer 190 can be programmably controlled (by FCEs) to feed these two signals back to phase detector 160 . The signal output by multiplexer 190 to work with rising edges is also the recovered clock output signal of the FIG. 4 circuitry. In addition to its other functions (described above), phase detector 160 passes the CDR data signal through a register that is clocked by one of the signals fed back from multiplexer 190 to produce the retimed data output signal of the FIG. 4 circuitry. This retimed data signal is the data signal that is further processed (using the recovered clock signal) by the apparatus of this invention.

[0056] Turning now to digital interpolator 182 , this circuitry receives the two pairs of clock signals that are output by circuitry 170 and, based on a control signal from circuitry 164 , selects the one signal in each pair with the better timing. Multiplexer 190 can be controlled to output the two signals selected by circuitry 182 for use (in lieu of the output signals of circuitry 180 ) as described above.

[0057] The reset signal shown in FIG. 4 has a purpose generally similar to the reset signal in FIG. 2 . Thus, when it is necessary or desirable to reset DPLL 150 (e.g., due to a loss-of-lock condition being detected), the reset signal is asserted to reset elements 162 , 164 , 180 , and 182 . Like the reset signal in FIG. 2 , the reset signal in FIG. 4 may come from PLD core 80 ( FIG. 1 ).

[0058] The power down signal in FIG. 4 is used to gate off all eight input clock signals when DPLL 150 is not going to be used. With all of the clock input signals gated off, the rest of the circuitry shown in FIG. 4 is not able to do any work and therefore consumes little or no power.

[0059] From the foregoing discussion, it will be apparent that after a suitable period of operation, the output signal of DPLL 150 will have substantially the same phase and frequency as the clock signal embedded in the CDR data received via driver 44 in FIG. 1 . The correct frequency is established by PLL 100 , which also produces a family of clock signals having that frequency and several different candidate phases. DPLL 150 picks the best candidate phases (the output signals of multiplexer circuitry 170 ) and then further refines the phase selection by making an appropriate adjustment or selection between the candidates. DPLL 150 can also take care of possible, relatively small differences in frequency between the PLL outputs and the clock information embedded in the incoming CDR data signal. In other words, DPLL 150 makes it possible for such relatively small frequency differences to exist without interfering with satisfactory CDR data transmission. This capability helps facilitate use of embodiments like that shown in FIG. 1A in which different sources 22 and 22 ′ are used for the actual CDR clock and the REFCLK signals.

[0060] An illustrative embodiment of deserializer 60 ( FIG. 1 ) is shown in more detail in FIG. 5 . In this embodiment deserializer 60 includes a multi-stage shift register 200 , a multi-stage parallel buffer register 210 , and programmable divider 220 . For example, each of registers 200 and 210 may have 20 stages and divider 220 may be programmable (using one or more FCEs) to divide the applied clock signal by any of several selectable values of J from 1 to 20. The serial, retimed, CDR data from DPLL 150 ( FIG. 4 ) is applied to the serial data input of shift register 200 . Shift register 200 also receives the recovered CLK output of DPLL 150 . Accordingly, shift register 200 shifts the serial CDR data into its several stages at the EMBCLK rate and in substantially perfect synchronism with the clock signal information embedded in the CDR signal.

[0061] Each time divider 220 has received the number of clock pulses equal to the value of J, the output signal of divider 220 switches to a level which enables buffer register 210 to respond to a clock signal by storing the contents of the horizontally adjacent stages of shift register 200 . In other words, shift register 200 stores data serially, and buffer register 210 periodically receives and stores the contents of shift register 200 in parallel. J is the length of each word (i.e., the number of bits per word) output in parallel by deserializer 60 . Another output signal of deserializer 60 is a clock signal divided by J (i.e., the CLK/J signal).

[0062] The J and reset signals shown in FIG. 5 may come from PLD core 80 ( FIG. 1 ). Like other reset signals described above, the reset signal in FIG. 5 is used to reset divider 220 when it is necessary or desirable reset the circuitry (e.g., due to detection of a loss-of-lock condition).

[0063] An illustrative embodiment of synchronizer 70 ( FIG. 1 ) is shown in more detail in FIG. 6 . In this embodiment synchronizer 70 includes RAM array 250 , write address logic 260 , and read address logic 270 . These elements operate as a first-in/first-out (“FIFO”) memory with independent reads and writes. Write address logic 260 may be basically a ring counter which counts (in a repeating cycle) the pulses in the CLK/J signal output by deserializer 60 ( FIG. 5 ). Accordingly, write address logic 260 addresses successive word storage locations in RAM array 250 in a repeating cycle in synchronism with pulses in the CLK/J signal. Assuming that the ENW signal has an appropriate level, RAM array 250 is enabled to receive and store data in signals from deserializer 60 . In this way, successive parallel data words available from deserializer 60 are stored in successive word storage locations in RAM array 250 . As has been said, writing into RAM array 250 is selectively enabled by the ENW signal, which may come from PLD core 80 ( FIG. 1 ), and which may be enabling as long as RAM array 250 is not producing a full output signal (described below).

[0064] Read address logic 270 may be basically another ring counter like write address logic 260 . Instead of counting clock pulses from deserializer 60 , however, read address logic 270 counts clock pulses (CORECLK) produced by PLD core 80 ( FIG. 1 ). Accordingly, read address logic 260 causes data words to be read from successive locations in RAM array 250 (which locations are addressed in a repeating cycle in synchronism with the CORECLK signal) as long as such reading is enabled by the ENR signal. Like the ENW signal, the ENR signal typically comes from PLD core 80 ( FIG. 1 ), and is typically enabling as long as RAM array 250 is not producing an empty output signal (described below). The data words read from RAM array 250 are applied to PLD core 80 .

[0065] From the foregoing, it will be apparent that RAM array 250 and its associated elements can operate to buffer data between two possibly different clock regimes (i.e., the CDR clock and a PLD core clock). For example, PLD core processing of data words can sometimes fall behind the incoming CDR data stream (e.g., during an interruption or slow-down in the CORECLK signal applied to synchronizer 70 ). Then the PLD can process data faster again to catch up to the incoming CDR data stream. RAM array 250 (or associated elements) may produce full and empty signals applied to PLD core 80 to tell the PLD core when the RAM array is approaching full or empty conditions, respectively. For example, in response to a full signal, PLD core 80 may speed up reading data from synchronizer 70 and/or the user may choose to have PLD core 80 respond to the full signal by using the ENW signal to stop further writing into RAM array 250 . In response to an empty signal PLD core 80 may slow down reading data from synchronizer 70 and/or the user may choose to have PLD core 80 respond to the empty signal by using the ENR signal to stop further reading from RAM array 250 .

[0066] The reset signal shown in FIG. 6 may be used to erase the contents of RAM array 250 whenever it is necessary or desirable to reset the circuitry (e.g., in response to detection of a loss-of-lock condition). Like the other reset signals described above, the reset signal in FIG. 6 may come from PLD core 80 ( FIG. 1 ).

[0067] FIG. 7 shows an illustrative embodiment of alternative CDR signaling apparatus 300 in accordance with the invention. Once again, although the major components 310 and 320 could be provided on the same integrated circuit, they are more typically portions of separate integrated circuits or circuit assemblies. In FIG. 12 , for example, component 320 could be associated with elements 500 / 600 , while component 310 could be associated with any other element(s) 1004 , 1006 , 1008 , and/or 1010 .

[0068] In apparatus 10 , PLD core 80 is associated with the receiver 40 of the CDR signal. In apparatus 300 , PLD core 80 is associated with the transmitter 320 of the CDR signal. Once again, to facilitate providing a programmable, PLD-based transmitter which can communicate with CDR receivers 310 having a wide range of expectations regarding the frequency of the CDR clock signal, apparatus 300 includes a reference clock signal source 22 in receiver 310 . Elements 22 , 24 , 26 , 42 , and 100 may all be similar to the correspondingly numbered elements in FIGS. 1 and 2 . Accordingly, the output signal of reference clock signal source 22 has frequency (REFCLK) related to the desired CDR clock signal frequency (EMBCLK) by the relationship given earlier, namely,

REFCLK*W=EMBCLK,

[0069] where again W is a convenient scale factor such as 0.5, 1, 2, 4, etc. This reference clock signal is transmitted to transmitter 320 as described above in connection with FIG. 1 . PLL 100 in transmitter 320 processes this signal as described above in connection with FIG. 2 to produce an output signal having a frequency which is precisely equal to the desired CDR clock frequency. This signal can be any one of the eight clock signals shown as outputs in FIG. 2 because the phase of this signal does not matter. (Conventional CDR signal receiver 350 , described in more detail below, is phase-generic and therefore not dependent on the received CDR signal having any particular phase.)

[0070] The CDR clock signal produced by PLL 100 (or some multiple of that signal as described in more detail below) is applied to synchronizer 330 and serializer 340 . Synchronizer 330 also receives data and clock signals from PLD core 80 . Synchronizer 330 uses the signals it receives to output the data from core 80 in synchronism with the CDR clock signal. Serializer 340 converts typically parallel data from synchronizer 330 to typically serial CDR data. The serial CDR data output by serializer 340 is transmitted to CDR signal receiver 350 via conventional differential driver 342 , leads 344 a and 344 b , and conventional differential driver 346 . (Elements 342 , 344 , and 346 may be respectively similar to elements 24 , 26 , and 42 in FIG. 1 . Also as in FIG. 1 the use of differential signaling for the CDR data is optional.) Conventional CDR signal receiver 350 uses the clock information embedded in the received CDR signal to extract the data from that signal in the conventional way.

[0071] Like the apparatus shown in FIG. 1 , the apparatus shown in FIG. 7 can be constructed to operate at any one of a wide range of CDR frequencies. Although not conventional for CDR signaling, the use of reference clock signal source 22 in receiver 310 to supply a reference clock signal to transmitter 320 facilitates providing generic transmitter apparatus that is programmable to support such a wide range of CDR frequencies.

[0072] FIG. 7A shows an alternative embodiment of circuitry of the type shown in FIG. 7 . The relationship between the FIG. 7 and FIG. 7A embodiments is similar to the relationship between the FIG. 1 and FIG. 1A embodiments. Thus FIG. 7A shows that reference clock signal source 22 ′ can be separate from receiver 310 ′. (In other respects source 22 ′ can be similar to source 22 .) As in the case of FIG. 1 A, providing a separate source 22 ′, which can be close to transmitter 320 , facilitates locating elements 310 ′ and 320 relatively far from one another because only the CDR data signal (and not also the REFCLK signal) must be transmitted across the relatively great distance between elements 310 ′ and 320 .

[0073] An illustrative embodiment of synchronizer 330 is shown in more detail in FIG. 8 . In this embodiment synchronizer 330 includes RAM array 360 , write address logic 370 , clock divider 380 , and read address logic 390 . RAM array 360 receives parallel data words from PLD core 80 ( FIG. 7 ) in synchronism with a CORECLK signal supplied by core 80 to write address logic 370 . Write address logic 370 may be similar to write address logic 260 in FIG. 6 and therefore addresses successive data word storage locations in RAM array 360 in a repeating cycle. Accordingly, successive data words supplied by PLD core 80 are stored in successive locations in RAM array 360 in a repeating cycle in synchronism with the CORECLK signal as long as writing is enabled by an ENW signal also supplied by core 80 . Core 80 typically supplies a write-enabling ENW signal as long as RAM array 360 is not producing a full signal.

[0074] Clock signal frequency divider 380 divides the CDRCLK signal output by PLL 100 ( FIG. 7 ) by J. The value of J is preferably a programmable parameter of the apparatus (e.g., stored in one or more FCEs). As in the earlier discussion of FIG. 5, J is an integer number equal to the number of bits in each parallel data word received by the FIG. 8 apparatus from PLD core 80 ( FIG. 7 ). The output signal of divider 380 is applied to read address logic 390 . Logic 390 may be similar to read address logic 270 in FIG. 6 . Accordingly, logic 390 addresses successive word storage locations in RAM array 360 in a repeating cycle for reading data words from those locations in synchronism with the output signal of divider 380 as long as reading is enabled by an ENR signal also supplied by core 80 . Core 80 typically supplies a read-enabling ENR signal as long as RAM array 360 is not producing an empty signal. Data read from RAM array 360 is applied in parallel to serializer 340 ( FIG. 7 ).

[0075] From the foregoing it will be seen that synchronizer 330 (like synchronizer 70 in FIG. 6 ) operates like a FIFO memory to buffer data between two possibly different clock regimes. In this case the data being buffered is data from PLD core 80 which is on its way to serializer 340 . As has already been alluded to, synchronizer 330 may produce full and empty signals to indicate to PLD core 80 when it is approaching a full or empty condition, respectively.

[0076] The reset signals shown in FIG. 8 may be used to erase the contents of RAM array 360 and reset divider 380 whenever it is necessary or desirable to reset the circuitry (e.g., in response to detection of a loss-of-lock condition). Like other reset signals mentioned herein, the reset signals in FIG. 8 may come from PLD core 80 ( FIG. 7 ).

[0077] An illustrative embodiment of serializer 340 is shown in more detail in FIG. 9 . In this embodiment serializer 340 includes parallel data register 400 and shift register 410 . Clock frequency divider 380 from FIG. 8 is also used again. Parallel data from RAM array 360 is applied to register 400 and stored in that register in response to a CDRCLK signal pulse gated by the output signal of divider 380 . (The CDRCLK signal shown in FIG. 9 can be the same as the similarly labeled signal in FIG. 8 .) The data stored in register 400 is transferred in parallel to shift register 410 in response to a CDRCLK signal pulse when the output signal of divider 380 indicates to register 410 that it should receive data during that CDRCLK signal pulse. During all CDRCLK signal pulses shift register 410 shifts data toward its serial data output lead. In particular, shift register 410 shifts its contents one stage toward its serial data output lead in response to each CDRCLK pulse. Accordingly, serializer 340 converts each parallel data word of J bits to serial CDR output data synchronized with the CDRCLK signal. The resulting CDR data signal is applied to differential driver 342 for transmission to receiver 310 in the same way that the CDR data signal in FIG. 1 is transmitted from source 30 to receiver 40 .

[0078] FIG. 10 shows a representative portion of an illustrative embodiment of a PLD 500 which includes all the features of above-described receiver 40 ( FIG. 1 ) and transmitter 320 ( FIG. 7 ), plus additional features that will be described below. Elements in FIG. 10 that are similar to previously described elements have the same reference numbers that have already been used for those elements. In FIG. 10 suffix letters “a” and “b” are added to facilitate unique reference to elements that occur more than once. Reference numbers in the 500 series are used in FIG. 10 for elements that were not specifically referenced in earlier FIGS. or that are added in FIG. 10 and therefore have no counterparts in earlier FIGS. Some elements are optionally modified or added in FIG. 10 to support signaling modes that are alternative to the illustrative CDR signaling mode discussed in connection with the earlier FIGS. For example, the reference clock signal supplied in FIG. 1 or FIG. 7 does not have to be a differential signal, but can instead be a single-ended signal. FIG. 10 shows apparatus for supporting that alternative. As another example, FIG. 10 shows apparatus for supporting non-CDR low voltage differential signaling (“LVDS”). (For additional background regarding non-CDR LVDS (referred to hereinafter as LVDS) see, for example, Nguyen et al. U.S. patent application Ser. No. 09/340,222, filed Jun. 25, 1999.)

[0079] It should be noted that to avoid overcrowding the drawing, FIG. 10 does not repeat all the circuitry shown in some of the earlier FIGS. For example, FIG. 10 does not show again the various reset and power down signals that are shown in some of the earlier FIGS. Nor does FIG. 10 show the ENW and ENR signals shown in certain earlier FIGS. It will be understood, however, that these signals are preferably present in the FIG. 10 circuitry.

[0080] Considering first the input aspects, FIG. 10 shows two representative input clock subcircuits (e.g., for the reference clock signals used in connection with CDR signaling or, in the case of PLL 100 b and associated circuitry, for alternatively receiving an LVDS clock signal). FIG. 10 also shows two representative data input subcircuits (e.g., for receiving CDR or LVDS signals). It will be understood that these various subcircuits can be used wholly or partly independently of one another or together in any of a wide range of combinations. For example, some subcircuits can be used for CDR signaling while other subcircuits are used for LVDS. It will also be understood that device 500 may include more of any or all of these various kinds of subcircuits.

[0081] A typical clock input subcircuit includes elements 42 a , 510 a , 512 , and 100 a . Element 510 a is a simple (i.e., non-differential) driver which can be programmably selected instead of differential driver 42 a when the incoming clock signal (e.g., a CDR reference clock signal) is single-ended rather than differential. Programmable logic connector (“PLC”) 512 allows programmable selection of the clock signal applied to PLL 100 a from among the output signal of drivers 42 a / 510 a and the clock signals on any of several global clock signal conductors 520 in PLD core 80 . One of these global clock signals may be selected when PLL 100 a is being used, for example, to produce a clock signal for LVDS transmission. When used for that purpose, the clock signal produced by PLL 100 a is output via LVDS differential driver 530 . Transmission (including LVDS transmission) is discussed more extensively later in this specification. PLL 100 b does not have an associated PLC 512 because PLL 100 b is not usable for LVDS transmission. PLL 100 b is, however, used for the clock signal that must accompany LVDS input. When used for CDR signaling as described earlier in this specification, PLL 100 a receives the output signal of driver 42 a or 510 a , and outputs eight phase-shifted candidate CDR clock signals. A similar group of eight signals can be output by PLL 100 b.

[0082] In FIG. 10 each PLL 100 may have a further output signal which is not shown in the earlier FIGS. This is a “loss of lock” signal on the lead 514 associated with each PLL. The loss of lock signal is a flag indicating whether or not the associated PLL has locked onto the applied clock signal. The loss of lock signal value indicating a locked condition can be produced, for example, after the output signal of PFD 110 ( FIG. 2 ) has been of relatively low magnitude for a predetermined time interval. Otherwise the loss of lock signal is produced with a value indicating that lock has been lost. The signals on leads 514 are applied to PLD core 80 for any desired use by the programmable logic of the core. For example, core 80 may be programmed to ignore data received from any subcircuit(s) for which loss of lock is currently being indicated and/or to produce the above-described reset signals for such subcircuit(s).

[0083] Each DPLL 150 has an associated PLC 540 for allowing selection of either of the two groups of eight signals output by PLLs 100 a and 100 b for application to that DPLL. Thus each DPLL 150 can be used with either of PLLs 100 . Each DPLL 150 has an associated input differential driver 44 (e.g., for receiving a CDR signal). Each DPLL 150 processes the applied CDR signal and candidate CDR clock signals to produce a final CDR clock signal which is applied to associated elements 60 and 220 as described earlier in this specification. Each DPLL 150 also produces a retimed CDR data signal which is applied to associated element 60 (although to avoid over-crowding FIG. 10 this is represented simply as a direct connection from the CDR data input driver 44 to the associated element 60 ). (It should be noted here that DPLLs 150 are not used at all for LVDS signaling. For this purpose each DPLL 150 has an associated PLC 518 for allowing a selected one of the eight output signals of PLL 100 b to bypass that DPLL and to be applied to the elements 60 and 220 associated with that DPLL.