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[0001] The invention relates generally to forming thin films over textured bottom electrodes, and more particularly to providing high permittivity dielectric and top electrode materials with near perfect conformability over memory cell bottom electrodes including hemispherical grain (HSG) silicon.
[0002] When fabricating integrated circuits, layers of insulating, conducting and semiconducting materials are deposited and patterned, layer by layer, to build up the desired circuit. Many types of circuits incorporate capacitors, each of which include a dielectric layer sandwiched two plates or electrodes. Memory chips such as dynamic random access memories (DRAMs), in particular, employ capacitors to store charge in memory cells. Each memory cell can represent one bit of data, where the capacitor can either be charged or discharged to represent logical states.
[0003] In accordance with the general trend in the semiconductor industry, integrated circuits are continually being scaled down in pursuit of faster processing speeds and lower power consumption. As the packing density of memory chips continues to increase, each capacitor in the more crowded memory cell must still maintain a certain minimum charge storage to ensure reliable operation of the memory cell without excessive refresh cycling. It is thus important that, with progressive generations of circuit design; capacitor designs achieve ever higher stored charge for the shrinking area of the chip (or footprint) allotted to each cell. Techniques have therefore been developed to increase the total charge capacity of the cell capacitor for a given footprint allotment.
[0004] The amount of charge stored on the capacitor is proportional to the capacitance, C=kk
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[0008] Relying solely on such structures for increasing the capacitance of the memory cell, however, becomes impractical with advancing generations of memory chip circuit designs. The surface area of a stud capacitor can theoretically be increased infinitely simply by increasing the height of the bottom electrode. Similarly, the depth of trench capacitors can be increased almost to the thickness of the substrate within which it is formed. Unfortunately, limits are imposed upon the height or depth of features in integrated circuits. As is well known in the art, it can be difficult to conformally coat, line or fill features with high steps using conventional deposition techniques. Additionally, increased topography on a chip can adversely affect the resolution of later photolithographic processes.
[0009] Rather than relying solely upon the height or depth of the cell capacitor, therefore, a microstructure can be added to further increase the surface area of the capacitor electrodes, by providing a textured or roughened surface to the macrostructural folds of the lower electrode. For example, polycrystalline conductive materials can be roughened by preferentially etching along grain boundaries, as disclosed, for example, in U.S. Pat. No. 3,405,801, issued to Han et al. Alternatively, U.S. Pat. No. 5,372,962, issued to Hirota et al., describes various selective etch processes for perforating a polysilicon layer.
[0010] Another class of electrode texturing techniques involve formation of hemispherical grained (HSG) silicon. Several methods for forming HSG silicon are known, including direct deposition, whereby deposited polysilicon selectively grows over nucleation sites, and redistribution anneal of amorphous silicon, whereby thermal energy causes silicon atoms to migrate about a surface and conglomerate about nucleation sites.
[0011] In order to fully realize the advantage of the increased surface area of textured bottom electrodes, the capacitor dielectric layer should conform closely to the surface of the bottom electrode. While the dielectric thickness (“d” of the capacitance formula set forth above) should be minimized in order to maximize capacitance, too thin a capacitor dielectric risks leakage current across the capacitor electrodes. Leakage current may result from pinholes in the dielectric and quantum tunneling effects, both of which phenomena are more likely to occur with thinner dielectrics. Thin capacitor dielectric layers are thus characterized by a low breakdown voltage, limiting the charge that may be stored on the bottom electrode before breakdown leakage occurs. Accordingly, capacitor dielectric layers may be characterized by a certain minimal thickness necessary to avoid breakdown, depending upon the selected dielectric material.
[0012] Referring to
[0013] As shown, the dielectric layer
[0014] Independently of variations across the workpiece, non-uniformity also results on a microlevel over rugged surfaces. In particular, at the neck region
[0015] If the dielectric
[0016] Due in part to such limitations on capacitance enhancement by increasing electrode surface area, more recent attention has been focused instead upon methods of increasing the dielectric constant (k) of the capacitor dielectric. Much effort has been aimed at integrating new dielectric materials having higher k values. High k materials include aluminum oxide (Al
[0017] Moreover, dramatic increases in k value for the capacitor dielectric allow use of smaller and simpler capacitor designs for a given stored charge requirement. Reducing the surface area needs for a cell capacitor can simplify the integration process and allow greater packing densities for future circuit designs.
[0018] Integrating high k materials into conventional process flows, however, has proven challenging. Some materials, such as Ta
[0019] Accordingly, a need exists for more effective methods of increasing the storage capacitance for integrated memory cells.
[0020] In satisfaction of this need, methods are provided herein for depositing dielectric and top electrode materials over textured bottom electrode surfaces. Advantageously, the methods attain high conformality, such that only the minimum required thickness of the lining layer need be formed on all surfaces. The methods enable deposition of high dielectric constant (high k) materials over hemispherical grain (HSG) silicon under conditions favorable to maintaining silicon electrodes.
[0021] In general, the methods comprise cycles of alternating reactant phases, wherein each phase has a self-limiting effect. Metal oxides and ternary materials having dielectric constants of greater than about 10 can be formed by alternately adsorbing self-terminated metal or silicon complex monolayers through ligand-exchange reactions. The ligands present on the adsorbed metal or silicon complex are then removed by presence of an oxygen-containing species, leaving OH groups and oxygen bridges for halide or organic monolayers. Examples are provided herein for simple binary metal oxides, ternary materials such as metal silicates and nanolaminates comprising alternating ultrathin dielectric layers of different compositions.
[0022] Advantageously, the methods enable forming uniformly thick dielectric layers over HSG silicon, desirably as thin as possible without inducing leakage current through the capacitor dielectric so formed. Moreover, the methods facilitate a combination of high k materials with high surface area, textured electrodes. Capacitance is thus maximized, facilitating further scaling of critical dimensions without loss of cell reliability.
[0023] Similar alternating chemistries are preferably employed to form top electrode materials over the conformal dielectric layers. Examples are provided herein for metal nitride barriers as well as elemental metal layers. Following formation of thin, conformal conductive layer(s) by the preferred methods, conventional deposition with reduced conformability can complete the desired thickness of the top electrode without sacrificing capacitance. Conformal capacitor dielectric and top electrodes formed by the preferred methods thus enable taking full advantage of the increased surface area afforded by textured bottom electrodes.
[0024] These and other aspects of the invention will be readily apparent to the skilled artisan in view of the description below, the appended claims, and from the drawings, which are intended to illustrate and not to limit the invention, and wherein:
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[0037] Though described in the context of certain preferred materials, it will be understood, in view of the disclosure herein, that the described methods and structures will have application to a variety of other materials suitable for capacitor dielectrics over rugged surfaces. Moreover, while illustrated for memory cell storage capacitors, the skilled artisan will readily appreciate application of the described methods to other roughened electrodes, such as the floating gate electrode of an Electrically Erasable Programmable Read Only Memory (EEPROM) device.
[0038] As discussed in the Background section above, coating capacitor electrodes, and particularly electrode structures bearing hemispherical grain (HSG) silicon, by conventional chemical vapor deposition (CVD) produces less than perfect conformality. While much research has been devoted to obtaining more conformal step coverage of semiconductor stepped features in general, it is very difficult to supply the same concentration of depositing species to all surfaces of such structures. In particular, it is difficult to supply the same concentration of depositing species at the upper surfaces of HSG grains as supplied to neck regions between grains. This problem is particularly exacerbated where the textured electrode conforms to a three-dimensional folding structure, such as the stacked and trench designs of
[0039] By providing almost perfect step coverage, the preferred embodiments advantageously obtain the minimum necessary thickness for the desired capacitor dielectric layers over all surfaces of HSG grains. Desirably, the methods of the preferred embodiment are less dependent upon the relative concentration of reactant species over grains as compared to confined grain intersections.
[0040] Moreover, the preferred embodiments provide methods of depositing high k materials in a manner that enables integration with high-surface area textured surfaces and with silicon electrodes, which is most often employed to produce microstructural roughness such as an HSG morphology. Rather than presenting a choice between high surface area textures over three-dimensional folding structures and high k dielectrics, the preferred embodiments allow the use of both techniques to achieve very high capacitance/footprint in a repeatable, production-worthy process.
[0041] The preferred embodiments provide exemplary processes for depositing Al
[0042] Further advantages of the preferred processes will be apparent from the discussion below.
[0043] Methods of Forming Conformal Capacitor Dielectrics
[0044]
[0045] Each pulse or phase of each cycle is preferably self-limiting in effect. In the examples set forth below, each of the phases are self-terminating (i.e., an adsorbed and preferably chemisorbed monolayer is left with a surface non-reactive with the chemistry of that phase). An excess of reactant precursors is supplied in each phase to saturate the structure surfaces. Surface saturation ensures reactant occupation of all available reactive sites (subject to physical size restraints, as discussed in more detail below), while self-termination prevents excess film growth at locations subject to longer exposure to the reactants. Systematic utilization of saturation through chemisorption, i.e., self-terminating chemistries, ensure excellent step coverage.
[0046] Prior to forming the dielectric layer, an integrated circuit is first partially fabricated to the point of constructing a capacitor lower or bottom electrode. Typically, the bottom electrode serves as a storage electrode in the memory cell. For purposes of the present description, however, the bottom electrode represents the first-formed capacitor electrode or plate, regardless of whether it serves as the storage or reference plate in the completed integrated circuit.
[0047] As illustrated in
[0048] After formation of the bottom electrode macrostructure, in either a stacked or trench arrangement, the bottom electrode is then provided
[0049] In an exemplary fabrication, conducted in a batch system sold under the trade name A600 UHV™ by ASM, International, Inc, the HSG silicon is formed by amorphous silicon deposition, seeding and redistribution anneal. A three-dimensional folding structure is formed of or coated with amorphous silicon. While in some processes, the amorphous silicon deposition can be conducted in situ within the same reaction chamber as the subsequent steps, in the illustrated embodiment, the folding amorphous silicon structure is formed prior transferring wafers to the A600 UHV™ system.
[0050] Within the preferred reactor, the amorphous silicon surface is seeded. In the illustrated embodiment, the temperature is raised to a level within the range of about 550° C. to 575° C. (e.g., about 560° C.) while the reactor pressure is preferably reduced to on the order of about 10
[0051] The HSG grains produced by the preferred process can range in size from about 50 Å to 750 Å, with more a typical range of about 300 Å to 500 Å. The process conditions affecting nucleation density and HSG silicon grain size are typically selected to leave grains largely separated from one another. Such an arrangement maximizes electrode surface area within the constraint of allowing most of the subsequent dielectric and top electrode layers to fit between the grains. As will be appreciated from the enlarged views of
[0052] As will be appreciated by the skilled artisan, the bottom electrode preferably serves as the storage node of a memory cell in a dynamic random access memory (DRAM) array. After fabrication, the bottom electrode is typically isolated from the bottom electrodes of other cells across the array, as shown in
[0053] The bottom electrode structure so formed is thereafter coated with high step coverage. In accordance with the preferred embodiments, the dielectric layer is formed by a periodic process in which each cycle forms no more than about one monolayer of dielectric material upon the workpiece in a self-limiting manner. Preferably, each cycle comprises at least two distinct phases, wherein each phase is a saturative reaction, i.e., self-limitingly, leaving no more than about one atomic monolayer of the desired dielectric material.
[0054] If necessary, the exposed surfaces of the bottom electrode (e.g., the HSG silicon of the preferred embodiments) are terminated
[0055] After initial surface termination
[0056] The metal-containing reactive species is preferably supplied in gaseous form, and is accordingly referred to hereinbelow as a metal source gas. The first chemistry is then removed
[0057] When the unreacted (or excess) reactants of the first chemistry have been removed
[0058] In other arrangements, the second chemistry may simply remove the ligand termination of the adsorbed metal complex monolayer formed in step
[0059] Desirably, the reaction
[0060] After a time period sufficient to completely saturate the surface of the metal-complex monolayer through chemisorption (or self-limiting reaction) of the second chemistry, the excess second chemistry is removed
[0061] In the illustrated embodiment, where two phases are alternated once the excess reactants and by-products of the second chemistry have been purged from the reaction chamber, the first phase of the ALD process is repeated. Accordingly, supplying
[0062] The two phases
[0063] With reference to
[0064] The illustrated cycle
[0065] In particular, after a first metal/silicon phase
[0066] Though the illustrated process includes four phases in each cycle
[0067] The second metal/silicon source gas in the third phase
[0068] The oxygen source gas of the fourth phase
[0069] For a roughly one-to-one ratio of the different metals or metal:silicon in the resultant dielectric, the cycle
[0070] Though both the binary and ternary processes are illustrated in
[0071] Methods of Forming Metal Oxide Dielectrics
[0072]
[0073] With reference now to
[0074] Surfaces upon which the dielectric material is to be formed are initially terminated to provide a surface that is reactive with the metal source gas. In the preferred embodiments, the exposed surfaces upon which deposition is desired include HSG silicon with OH terminating tails (see
[0075] Most preferably, the metal phase
[0076] After a sufficient time for the metal source gas to saturate surfaces of the bottom electrode, shutting off the flow of the metal source gas ends the metal pulse
[0077] During the pulse
[0078] In particular, the metal-containing species provided to the workpiece is self-terminating such that the adsorbed complex surface will not further react with the metal source gas. In the examples set forth below, TMA (Table I) leaves a monolayer of methyl-terminated aluminum. Tantalum ethoxide (Table II) leaves a monolayer of ethoxide tantalum. Similarly, other volatile metal halides will leave halide-terminated surfaces, and metallorganic precursors will leave surface terminated with organic ligands. Such surfaces do not further react with the metal source or other constituents of the reactant flow during the metal source gas pulse
[0079] In a second phase
[0080] During the oxygen pulse
[0081] In particular, the oxygen source gas reacts with the ligand of the metal complex chemisorbed onto the workpiece surface during the previous pulse of metal source gas. The reaction is also surface limiting or terminating, since the oxidant during the pulse
[0082] The metal phase
[0083] The cycle
[0084] The tables below provide exemplary process recipes for forming metal oxide and ternary dielectric layers suitable for capacitor dielectric applications in DRAM memory cells for ultra large scale integrated processing. The dielectrics are particularly suited to deposition over HSG silicon. Each of the process recipes represents one cycle in a single-wafer process module. In particular, the illustrated parameters were developed for use in the single-wafer ALD module commercially available under the trade name Pulsar 2000™, available commercially from ASM Microchemistry Ltd. of Finland.
[0085] Note that the parameters in the tables below are exemplary only. Each process phase is desirably arranged to saturate the bottom electrode surfaces. Purge steps are arranged to remove reactants between reactive phases from the reaction chamber. The illustrative ALD processes achieve better than about 95% thickness uniformity, and more preferably greater than about 98% thickness uniformity over HSG grains with average gain sizes of about 400 Å. Thickness uniformity, as used herein, is defined as the percentage of a thickness minimum as a percentage of the thickness maximum. In view of the disclosure herein, the skilled artisan can readily modify, substitute or otherwise alter deposition conditions for different reaction chambers and for different selected conditions to achieve saturated, self-terminating phases at acceptable deposition rates.
[0086] Advantageously, the ALD processes described herein are relatively insensitive to pressure and reactant concentration, as long as the reactant supply is sufficient to saturate the textured surfaces. Furthermore, the processes can operate at low temperatures. Workpiece temperature is preferably maintained throughout the process between about 150° C. and 350° C. to achieve relatively fast deposition rates while conserving thermal budgets. More preferably, the temperature is maintained between about 220° C. and 300° C., depending upon the reactants. Pressure in the chamber can range from the milliTorr range to super-atmospheric, but is preferably maintained between about 1 Torr and 500 Torr, more preferably between about 1 Torr and 10 Torr.
TABLE I Al Carrier Reactant Flow Flow Temperature Pressure Time Phase (sccm) Reactant (sccm) (° C.) (Torr) (sec) metal 400 TMA 20 300 5 0.1 purge 400 — — 300 5 0.2 oxidant 400 H 40 300 5 0.1 purge 400 — — 300 5 0.6
[0087] Table I above presents parameters for ALD of an aluminum oxide (Al
[0088] In the first phase of the first cycle, TMA chemisorbs upon the HSG silicon surfaces of the bottom electrode. The metal source gas preferably comprises a sufficient percentage of the carrier flow, given the other process parameters, to saturate the bottom electrode surfaces. A monolayer of aluminum complex is left upon the HSG silicon surfaces, and this monolayer is self-terminated with methyl tails.
[0089] After the TMA flow is stopped and purged by continued flow of carrier gas, a pulse of H
[0090] In the next cycle, the first phase introduces TMA, which readily reacts with the surface of the aluminum oxide monolayer, again leaving a methyl-terminated aluminum layer above the first metal oxide layer. The second phase of the second cycle is then as described with respect to the first cycle. These cycles are repeated until the desired thickness of aluminum oxide is formed.
[0091] In the illustrated embodiment, carrier gas continues to flow at a constant rate during both phases of each cycle. It will be understood, however, that reactants can be removed by evacuation of the chamber between alternating gas pulses. In one arrangement, the preferred reactor incorporates hardware and software to maintain a constant pressure during the pulsed deposition. The disclosures of U.S. Pat. No. 4,747,367, issued May 31, 1988 to Posa and U.S Pat. No. 4,761,269, issued Aug. 2, 1988 to Conger et al., are incorporated herein by reference.
[0092] Radicals provided by plasma generators can facilitate deposition of metal-containing layers at the low temperatures of ALD processing. Structures and methods of depositing layers with radical enhancement are provided in patent application having Ser. No. 09/392,371, filed Sep. 8, 1999 and entitled IMPROVED APPARATUS AND METHOD FOR GROWTH OF A THIN FILM, the disclosure of which is incorporated by reference hereinabove. Another exemplary ALD process flow is provided in U.S. Pat. No. 5,916,365 to Shermnan, issued Jun. 29, 1999, the disclosure of which is incorporated herein by reference.
TABLE II Ta Carrier Reactant Tem- Flow Flow perature Pressure Time Phase (sccm) Reactant (sccm) (° C.) (Torr) (sec) metal 400 Ta(OCH 40 220 5 1 purge 400 — — 220 5 1 oxidant 400 O 100 220 5 1 purge 400 — — 220 5 2
[0093] Table II above presents parameters for ALD of a tantalum oxide (Ta
[0094] Following formation of the barrier layer, Ta
[0095] In the first phase of the first cycle, tantalum ethoxide chemisorbs upon the nitridized surfaces of the HSG silicon. The metal source gas preferably comprises a sufficient percentage of the carrier flow, given the other process parameters, to saturate the nitride-coated HSG silicon surfaces. A monolayer of tantalum complex is left upon the textured surfaces, and this monolayer is self-terminated with ethoxide tails.
[0096] After the metal source gas flow is stopped and purged by continued flow of carrier gas, a pulse of ozone is supplied to the workpiece. Ozone preferably comprises a sufficient percentage of the carrier flow, given the other process parameters, to saturate the surface of the metal-containing monolayer. The ozone readily reacts with the ethoxide-terminated surface of the metal-containing monolayer in a ligand-exchange reaction, forming a monolayer of tantalum oxide (Ta
[0097] In the next cycle, the first phase introduces tantalum ethoxide, which readily reacts with the surface of the tantalum oxide monolayer, again leaving an ethoxide-terminated tantalum layer. The second phase of the second cycle is then as described with respect to the first cycle. These cycles are repeated until the desired thickness of tantalum oxide is formed. Preferably, between about 80 and 200 cycles are conducted to grow between about 40 Å and 100 Å of Ta
[0098] In the illustrated embodiment, carrier gas continues to flow at a constant rate during both phases of each cycle. It will be understood, however, that reactants can be removed by evacuation of the chamber between alternating gas pulses. In one arrangement, the preferred reactor incorporates hardware and software to maintain a constant pressure during the pulsed deposition. The disclosures of U.S. Pat. No. 4,747,367, issued May 31, 1988 to Posa and U.S. Pat. No. 4,761,269, issued Aug. 2, 1988 to Conger et al., are incorporated herein by reference.
[0099] An amorphous Ta
TABLE III Ta Carrier Reactant Flow Flow Temperature Pressure Time Phase (sccm) Reactant (sccm) (° C.) (Torr) (sec) metal 400 TaCl 40 300 5 0.5 purge 400 — — 300 5 0.5 oxidant 400 H 40 300 5 0.5 purge 400 — — 300 5 0.5
[0100] Table III above presents parameters for another ALD process for depositing tantalum oxide (Ta
[0101] In the first phase of the first cycle, tantalum chloride chemisorbs upon the silicon nitridized surfaces of the HSG. The metal source gas preferably comprises a sufficient percentage of the carrier flow, given the other process parameters, to saturate the nitride-coated HSG silicon surfaces. A monolayer of tantalum complex is left upon the textured surfaces, and this monolayer is self-terminated with chloride tails.
[0102] After the TaCl
[0103] In the next cycle, the first phase introduces TaCl
[0104] As mentioned above, the chamber can be evacuated to remove reactants between pulses, rather than purged by a steady carrier gas flow as shown, though inter-pulse purging is preferred.
[0105] An amorphous Ta
TABLE IV ZrO Carrier Reactant Flow Flow Temperature Pressure Time Phase (sccm) Reactant (sccm) (° C.) (Torr) (sec) metal 400 ZrCl 5 300 5 0.5 purge 400 — — 300 5 3 oxidant 400 H 40 300 5 2 purge 400 — — 300 5 6
[0106] Table IV above presents parameters for ALD of zirconium oxide (ZrO
[0107] In this case, the metal monolayer formed in the metal phase is self-terminated with chloride, which does not readily react with excess ZrCl
[0108] Preferably, between about 30 and 80 cycles are conducted to grow between about 20 Å and 60 Å of ZrO
TABLE V TiO Carrier Reactant Flow Flow Temperature Pressure Time Phase (sccm) Reactant (sccm) (° C.) (Torr) (sec) metal 400 TiCl 20 300 5 0.5 purge 400 — — 300 5 3 oxidant 400 H 40 300 5 2 purge 400 — — 300 5 6
[0109] Table V above presents parameters for ALD of titanium oxide (TiO
[0110] As described with respect to ZrO
[0111] In this case, the metal monolayer formed in the metal phase is self-terminated with chloride, which does not readily react with TiCl
[0112] Preferably, between about 30 and 80 cycles are conducted to grow between about 20 Å and 60 Å of TiO
[0113] Method of Forming Ternary Dielectric Layers
[0114] As discussed with respect to
[0115] With reference to
[0116] As illustrated, the process comprises four phases to each cycle, wherein each phase comprises a reactant phase and a purge phase. A first metal or silicon phase