DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0101] Preferred embodiments of the present invention will hereinafter be described in detail with reference to the accompanying drawings.

[0102] FIGS. 1 through 5 respectively illustrate upward compatible memory cards based on multi media cards, in which FIGS. 1(A), 2(A), 3(A), 4(A), and 5(A) show terminal surfaces, and FIGS. 1(B), 2(B), 3(B), 4(B), and 5(B) illustrate chip mounting surfaces, respectively.

[0103] A memory card (multi media card-based memory card) MC1 based on a multi media card, which is basic to these memory cards, will first be explained with reference to FIG. 6. A card substrate (also called a “multi media card-based card substrate”) 1 of the multi media card-based memory card MC1 is configured in such a manner that seven connector terminals 2 respectively identical in shape to one another and rectangular are provided at equal intervals on a terminal surface of a substrate comprising a resin substrate composed of a glass epoxy resin or the like, and connecting pads 3 are formed on a mounting surface thereof in a one-to-one correspondence with the connector terminals 2. Each connecting pad 3 is formed of a conductive pattern such as aluminum, copper, or a ferro-alloy or the like. Each of the connector terminals 2 is formed by applying gold plating, nickel plating or the like to a conductive pattern such as aluminum, copper, or the ferro-alloy or the like. Electrical connections between the connecting pads 3 and the connector terminals 2 are conducted by unillustrated wiring patterns on the card substrate 1 and through holes which bring the front and back of the card substrate 1 into conduction.

[0104] For example, electrically rewritable flash memory chips 4 and a controller chip 5 for controlling the flash memory chip 4 are mounted on the mounting surface of the card substrate 1. The controller chip 5 controls a read/write operation effected on each flash memory chip 4 in accordance with instructions given from outside through each connector terminal 2. When data security is taken into consideration, the controller chip 5 may further be provided with the a security function for encrypting or encoding data written into its corresponding flash memory chip 4 and decrypting or decoding the data read out from the flash memory chip 4.

[0105] The controller chip 5 has a shape long along the direction of an arrangement of the connector terminals 2 and includes a plurality of connector interface terminals 5Pi electrically connected to their corresponding connector terminals 2 through the connecting pads 3 on the connector terminal 2 side, and a plurality of memory interface terminals 5Pj electrically connected to their corresponding memory chips 4 on the memory chip 4 side. Each of the memory chips 4 has a plurality of controller interface terminals 4Pk electrically connected to the corresponding controller chip 5 on the controller chip 5 side. The connecting pads 3 are connected to their corresponding connector interface terminals 5Pi of the controller chip 5 by bonding wires 7. The memory interface terminals 5Pj of the controller chip 5 are electrically connected to their corresponding controller interface terminals 4Pk of each memory chip 4 by bonding wires 8. Reference numeral 9 indicates a relay pattern.

[0106] Further, the card substrate 1 has test terminals 10 electrically connected to the controller chip 5 and each of the memory chips 4 by bonding wires (or wiring patterns) 11. The card substrate 1 is attached and fixed to a casing 12 with its mounting surface directed inwardly. The mounting surface of the card substrate 1 is covered with the casing 12 for its protection and the terminal surface thereof is exposed from the casing 12. Incidentally, one example of the electrical connections made by the bonding wires 7, 8 and 11 is shown in the drawing, and the unillustrated terminals are also electrically connected by their corresponding bonding wires or the like in the same manner as described above.

[0107] Now, terminal numbers #1 through #7 are assigned to the connector terminals 2 on the terminal surface for convenience. In a multi media card mode, #1 serves as a reserve terminal (open or fixed to a logical value “1”), #2 functions as a command terminal (which performs a command input and a response signal output), #3 and #6 serve as circuit's ground voltage (ground) terminals, #4 serves as a source voltage supply terminal, #5 serves as a clock input terminal, and #7 serves as a data input/output terminal, respectively. In an SPI (Serial Peripheral Interface) mode, #1 serves as a chip select terminal (negative logic), #2 serves as a data input terminal (for the input of data and commands from a host device to a card), #3 and #6 serve as the circuit's ground voltage (ground) terminals, #4 serves as the source voltage supply terminal, #5 serves as the clock input terminal, and #7 serves as a data output terminal (for the output of data and status from the memory card to the host device), respectively. The multi media card mode is an operation mode suitable for a system in which a plurality of multi media cards are used simultaneously. The identification of each multi media card is done by a card identification ID (relative address) set to its multi media card by the unillustrated host device. The SPI mode is most suitable for application to a simple and inexpensive system, and the operation of each multi media card is selected by a chip select signal supplied to the connector terminal of #1. Even in the case of any of the operation modes, the controller chip 5 performs access control of a memory chip and control for interface with the host device in response to a command given from the host device.

[0108] An upward compatible memory card MC2 of a type wherein data terminals are set to four bits with respect to the multi media card, is shown in FIG. 1 by way of example. The present memory card MC2 is different from the memory card MC1 in that nine connector terminals 2 and connecting pads 3 are laid out respectively. The terminal numbers #1 through #7 are identical in layout configuration to the multi media card-based memory card MC1, and the two connector terminals added in this way are defined as terminal numbers #8 and #9 respectively.

[0109] The connector terminals 2 of #1 through #7 constitute a connector terminal sequence corresponding to a first row or sequence with respect to a card substrate 1A. The added connector terminals 2 of #8 and #9 constitute a connector terminal sequence corresponding to a second row or sequence placed so as to be spaced away from the connector terminal sequence corresponding to the first sequence. The connector terminals 2 of #8 and #9 are identical in size to other connector terminals 2. The connector terminal sequence corresponding to the first sequence and the connector terminal sequence corresponding to the second sequence are provided so that the layouts of their connector terminals are shifted from one another as viewed in their row or sequence directions. In other words, the connector terminals 2 of #1 and #9, and the connector terminals 2 of #7 and #8 are laid out in staggered form.

[0110] The present memory card MC2 is configured in such a manner that the terminals #2 through #7 are assigned to the same functions as the multi media card mode of the multi media card-based memory card MC1, the terminal #1, which was used as the reserve terminal in the corresponding multi media card mode, is defined as a data terminal DATA3 corresponding to a fourth bit, and the added terminals #8 and #9 are respectively defined as a data terminal DATA1 corresponding to a second bit, and a data terminal DATA2 corresponding to a third bit. A data terminal DATA0 corresponding to a first bit corresponds to the same terminal #7 as that in the multi media card mode. Thus, the present memory card MC2 is different from the memory card MC1 in that the input/output of data is allowed in 4-bit parallel in the multi media card mode of the memory card MC1.

[0111] Further, the memory card MC2 has a downward compatible mode with respect to the multi media card-based memory card MC1. Namely, the controller chip 5A has a one-bit mode which makes use of one bit #7 of the four-bit data terminals #1, #7, #8 and #9, and a four-bit mode which performs a four-bit parallel input/output using the four-bit data terminals #1, #7, #8 and #9. The one-bit mode is an operation mode which allows the memory card MC2 to operate as the multi media card-based memory card MC1.

[0112] The operation mode may be set in response to the state of a predetermined connector terminal or the state of the input of a command from the predetermined connector terminal. For example, when the memory card MC2 is loaded in the card socket of the multi media card-based memory card MC1, the terminals #8 and #9 reach floating. Therefore, when power is turned on, the controller chip 5A may detect floating states of both of the terminals #8 and #9 or a floating state of one thereof to set the one-bit mode to the memory card MC2. When the memory card MC2 having the nine connector terminals 2 is fitted in its dedicated card socket, the terminals #8 and #9 are conductive to a socket terminal of the card socket. Therefore, when power is turned on, the controller chip 5A may detect the supply of a specific signal or command from the host device to both or one of at least the terminals #8 and #9 to set the four-bit mode to the corresponding memory card MC2.

[0113] The controller chip 5A is different from the controller chip 5 in that the number of data input/output terminals connected to connecting pads 3 is four. Other configurations are identical to those shown in FIG. 6. Circuit elements each having the same function are identified by the same reference numerals and their detailed description will therefore be omitted.

[0114] Another upward compatible memory card MC3 in which data terminals are set to four bits with respect to the multi media card, is illustrated in FIG. 2 by way of example. A card substrate 1B of the memory card MC3 is different from that of the memory card MC2 in that data terminals corresponding to the terminal numbers #8 and #9 are different in layout and size from each other. The data terminal of #8 is completely built or set in a terminal row or sequence corresponding to a first sequence and slightly reduced in width as compared with other connector terminals 2. The data terminal of #9 is laid out at and changed to a position placed outside a data terminal of #1 and placed in a state of being nested toward it. Other configurations are similar to those shown in FIG. 1. Circuit elements each having the same function are identified by the same reference numerals and their detailed description will therefore be omitted.

[0115] An upward compatible memory card MC4 in which data terminals are set to eight bits with respect to the multi media card, is illustrated in FIG. 3 by way of example. The present memory card MC4 is different from the memory card MC1 in that thirteen connector terminals 2 and connecting pads 3 are respectively laid out. The terminal numbers #1 through #7 are identical in layout configuration to those of the multi media card-based memory card MC1, and the added six connector terminals are defined as terminal numbers #8 through #13.

[0116] The connector terminals 2 of #1 through #7 constitute a connector terminal sequence corresponding to a first row or sequence with respect to a card substrate IC. The added connector terminals 2 of #8 through #13 constitute a connector terminal sequence corresponding to a second row or sequence placed so as to be spaced away from the connector terminal sequence corresponding to the first sequence. The connector terminals 2 of #8 through #13 are identical in size to other connector terminals 2. The connector terminal sequence corresponding to the first sequence and the connector terminal sequence corresponding to the second sequence are provided so that the layouts of their connector terminals are shifted from one another as viewed in their row or sequence directions. If attention is focused on terminal-to-terminal regions or areas of the connector terminals 2, then an arrangement of terminal-to-terminal areas of the connector terminal sequence corresponding to the first sequence and an arrangement of terminal-to-terminal areas of the connector terminal sequence corresponding to the second sequence are shifted from one another as viewed in their sequence directions. In short, the connector terminals corresponding to the first sequence and the second sequence are disposed in staggered form between the rows or sequences in a manner similar to the memory card MC2 shown in FIG. 1.

[0117] The present memory card MC4 is configured in such a manner that the terminals #2 through #7 are assigned to the same functions as the multi media card mode of the multi media card-based memory card MC1, the terminal #1, which was used as the reserve terminal in the corresponding multi media card mode, is defined as a data terminal DATA3 corresponding to a fourth bit, and the added terminals #8, #9, #10, #11, #12 and #13 are respectively successively defined as a data terminal DATA1 corresponding to a second bit, a data terminal DATA4 corresponding to a fifth bit, a data terminal DATA6 corresponding to a seventh bit, a data terminal DATA7 corresponding to an eighth bit, a data terminal DATA5 corresponding to a sixth bit, and a data terminal DATA1 corresponding to a second bit. A data terminal DATA0 corresponding to a first bit corresponds to the same terminal #7 as that in the multi media card mode. Thus, the present memory card MC4 is different from the memory card MC1 in that the input/output of data is allowed in 8-bit parallel in the multi media card mode of the memory card MC1.

[0118] Further, the memory card MC4 has a downward compatible mode with respect to the multi media card-based memory card MC1. Namely, a controller chip 5B has a one-bit mode which makes use of one bit #7 of the eight-bit data terminals #1 and #7 through #13, a four-bit mode which performs a four-bit parallel input/output using the four bits #1, #7, #8 and #13 of the eight-bit data terminals #1 and #7 through #13, and an eight-bit mode which performs an eight-bit parallel input/output using the eight-bit data terminals #1 and #7 through #13. The one-bit mode is an operation mode which allows the memory card MC4 to operate as the multi media card-based memory card MC1. The four-bit mode is the same operation mode as the four-bit modes for the memory cards MC2 and MC3.

[0119] The operation mode may be set in response to the state of a predetermined connector terminal or the state of the input of a command from the predetermined connector terminal. For example, when the memory card MC4 is loaded in the card socket of the multi media card-based memory card MC1, the terminals #8 through #13 reach floating. Therefore, when power is turned on, the controller chip 5B may detect floating states of the connector terminals 2 for both of the data terminals DATA1 and DATA2 at which a difference from the four-bit mode can be recognized, or a floating state of the connector terminal 2 for one thereof (by exclusively using software or exclusively using a hardware configuration) to set the one-bit mode to the memory card MC on a software or hardware basis.

[0120] When the memory card MC4 is fitted in the card socket of the memory card MC2 shown in FIG. 1, the terminals #9 through #12 are brought to floating. Therefore, when power is turned on, the controller chip 5B may detect floating states of all or some connector terminals 2 for the data terminals DATA4 through DATA7 on a software or hardware basis to set the four-bit mode to the memory card MC4.

[0121] On the other hand, when the memory card MC4 is loaded in its dedicated card socket, the terminals #9 through #12 are conductive to a socket terminal of the card socket. Therefore, when power is turned on, the controller chip 5B may detect the supply of a specific signal or command from a host device to all or some of at least the data terminals DATA4 through DATA7 to set the eight-bit mode to the corresponding memory card MC4.

[0122] The controller chip SB is different from the controller chip 5 in that the number of data input/output terminals connected to the connecting pads 3 is eight. Other configurations are identical to those shown in FIG. 6. Circuit elements each having the same function are identified by the same reference numerals and their detailed description will therefore be omitted.

[0123] Another upward compatible memory card MC5 in which data terminals are set to eight bits with respect to the multi media card, is illustrated in FIG. 4 by way of example. A card substrate 1D of the memory card MC5 is different from that of the memory card MC4 in that the layout of the connector terminals 2 of the terminal numbers #8 and #13 is similar to the memory card MC3 shown in FIG. 2. A data terminal of #13 is completely built or set in a terminal row or sequence corresponding to a first sequence and slightly reduced in width as compared with other connector terminals 2. A data terminal of #8 is laid out at and changed to a position placed outside a data terminal of #1 and placed in a state of being nested toward it. Other configurations are similar to those shown in FIG. 3. Circuit elements each having the same function are identified by the same reference numerals and their detailed description will therefore be omitted.

[0124] A further upward compatible memory card MC6 in which data terminals are set to eight bits with respect to the multi media card, is illustrated in FIG. 5 by way of example. A card substrate 1E of the memory card MC6 is different from that of the memory card MC4 shown in FIG. 3 in that the shapes of the connector terminals 2 of the terminal numbers #8 and #13 extend so as to contain the connector terminals 2 of the terminal numbers #8 an #13 shown in FIG. 4. Namely, the connector terminal 2 of the terminal number #13 extends to a position where it perfectly adjoins a connector terminal #7 placed in the first sequence and provided at one end as viewed in the row or sequence direction, of the connector terminal sequence. The connector terminal 2 of the terminal number #8 extends to a position where it partly overlaps with a connector terminal #1 placed in the first sequence and included in the connector terminal sequence as viewed in the sequence direction and adjoins the connector terminal #1. Other configurations are similar to those shown in FIG. 3. Circuit elements each having the same function are identified by the same reference numerals and their detailed description will therefore be omitted.

[0125] As is apparent from the above, the memory cards MC2 through MC6 shown in FIGS. 1 through 5 respectively have upward compatibility with respect to the multi media card-based memory card MC1 or the unillustrated known multi media card. For example, a low-order or downward memory card can be used by being inserted into a card socket of a high-order or upward memory card. Further, each of the memory cards MC2 through MC6 has also downward compatibility that, for example, an upward memory card can be used by being inserted into a socket of a downward memory card. Described in details, the memory cards MC2 and MC3 shown in FIGS. 1 and 2 have upward-downward compatibility in a relationship with the memory card MC1 shown in FIG. 6. The memory card MC4 shown in FIG. 3 has upward-downward compatibility in a relationship with the memory cards MC1 and MC2 shown in FIGS. 6 and 1. The memory card MC5 shown in FIG. 4 has upward-downward compatibility in a relationship with the memory cards MC1 and MC3 shown in FIGS. 6 and 2. Since the memory card MC6 shown in FIG. 5 has a connector terminal arrangement including complementarity between the arrangement of the connector terminals 2 of the memory card MC4 shown in FIG. 3 and the arrangement of the connector terminals 2 of the memory card MC5 shown in FIG. 4, it can be ranked as an almighty card having upward-downward compatibility even in a relationship with any of FIGS. 1, 2, 3, 4 and 6.

[0126] FIG. 7 shows the state in which the corresponding memory card MC6 is loaded in a card socket corresponding to the almighty card MC6. The card socket 22 has socket terminals 22A which protrude toward the back or inner portion so as to correspond to their connector terminals 2. Since the plural-sequence layout of the form typified by the staggered fashion is adopted, a configuration or structure in which the amounts of protrusions of the socket terminals 22A of the card socket 22 are changed and they are laid out in tandem, can be adopted with relative ease for the arrangement of the connector terminals 2. Contacts with the connector terminals 2 are tips or leading ends (▪ marks) of the socket terminals 22A.

[0127] FIG. 8 shows the state in which the almighty memory card MC6 is loaded in a card socket 21 corresponding to the multi media card-based memory card MC1 shown in FIG. 1 or an unillustrated multi media card. As described above, the memory card MC6 is set to the one-bit mode, so that it can perform the same operation as the multi media card-based memory card MC1 or the unillustrated multi media card.

[0128] FIG. 9 shows the state in which the almighty memory card MC6 is loaded in a card socket 22 corresponding to the multi media card-based memory card MC3 shown in FIG. 2. As described above, the memory card MC6 is capable of performing the same operation as the memory card MC3 by being set to the four-bit mode.

[0129] Although not illustrated in the drawing in particular, the memory cards MC1 through MC5 shown in FIG. 6 and FIGS. 1 through 4 can respectively be operated in predetermined operation modes even if they are loaded in the card socket 22 shown in FIG. 7. The thickness of each card is substantially equal to a thickness of 1.4 mm of the multi media card. Compatibility available even if the memory cards are mutually inserted into any other type of card sockets, can be implemented.

[0130] FIG. 10 is a schematic block diagram of a data processing system having the card socket 22 shown in FIG. 7. The data processing system shown in the same drawing has a card socket 22 in which the memory card MC6 capable selecting the one-bit mode, four-bit mode or eight-bit mode can be fitted. The card socket 22 has a plurality of socket terminals 22A connected to connector terminals 2 of a memory card MC mounted as shown in FIG. 7. The data processing system is provided with a card interface controller 30 capable of selectively setting the one-bit mode, four-bit mode or eight-bit mode to the memory card MC through the socket terminals 22A. The card interface controller 30 is placed under the control of a host control device 31. The host device 31 is a circuit like a CPU board, for example, and includes a microprocessor and a work RAM for the microprocessor. Further, the host device 31 performs interface control of commands or data with the card interface controller 30 through a bus and control for setting the operation mode to the memory card MC loaded in the card socket 22. Thus, any of the memory cards MC1 through MC6 can be used.

[0131] Incidentally, a plurality of types of memory cards can similarly be applicable even to a data processing system having a card socket of a memory card MC2 or MC3 although not shown in the drawing.

[0132] In the memory cards MC2 through MC6 shown in FIGS. 1 through 5, the back-and-forth arrangement of the connector terminals 2 in two rows or lines takes into consideration the prevention of a power-to-power short. In the aforementioned examples, no terminals are provided behind the terminals of #4 used as the power supply connector terminals. At portions where the connector terminals 2 are placed back and forth as viewed in a row direction as shown in FIG. 7 by way of example, the socket terminals of the card socket 22 respectively include short terminals 22As and long terminals 22Al alternately compactly laid out at pitches each equal to half of that of each connector terminal 2. On the other hand, if no connector terminal is provided behind, then no long socket terminals 22Al are placed next door to each other on both sides of a socket terminal 22Aa corresponding to the connector terminal of #4 for the source voltage (Vdd) supply as shown in FIG. 7 by way example.

[0133] On the other hand, now consider a memory card MC7 in which data terminals of #10 and #11 are placed behind a connector terminal of #4 for the supply of a source voltage (Vdd) as illustrated in FIG. 11(A) by way of example. In a card socket 23 corresponding to the memory card MC7, long socket terminals 23Ab are disposed next to socket terminals 23Aa corresponding to the connector terminal of #4.

[0134] When the memory card MC7 is inserted into the card socket 23, contacts (▪ marks) of the socket terminals 23Ab are respectively brought into sliding contact with the surface of the connector terminal of #4 to which the source voltage Vdd is inputted, and the surface of a connector terminal of #3 to which a ground voltage is inputted. When, at this time, a socket terminal 23Aa supplied with the source voltage Vdd is made conductive to the connector terminal of #4, and a socket terminal 23Ac supplied with a circuit's ground voltage Vss is rendered conductive to the connector terminal of #3, the source voltage Vdd and the ground voltage Vss are short-circuited through a contact of 23Aa, #4, a contact of 23Ab, #3 and a contact of 23Ac as shown in FIG. 11(C).

[0135] The non-provision of the connector terminal behind the terminal of #4 used as the power supply connector terminal as shown in FIG. 7 by way of example allows prevention of the possibility of such a power short beforehand.

[0136] As a countermeasure against the power short, connector terminal in which broad terminal-to-terminal distances are respectively set to a portion where the connector terminal faces a connector terminal sequence corresponding to a second sequence, may be provided in a connector terminal sequence corresponding to a first sequence as viewed in a memory card inserting direction as shown in FIG. 12 by way of example. In brief, relatively large chamfered portions may be formed at the corners of the rears of the connector terminals 2A.

[0137] As another countermeasure against the power short, a distance D1 extending from a leading end of each of contacts of short socket terminals 23Aa and 23Ac to a base end of a contact of a long socket terminal 23Ab may be set greater than a width dimension B1 of each of connector terminals of #3 and #4 as shown in FIG. 13 by way of example. Further, the thickness of the socket terminal 23Ab may sufficiently be set smaller than interval dimensions of the connector terminals of #3 and #4. However, when it is desired to prevent the power short according to dimensional provisions, a processing error and an assembly error occur. Further, since it is impossible to regard the memory card itself as a rigid body, it is advisable to take the countermeasures shown in FIGS. 7 and 12 for the purpose of preventing the power short with a high degree of reliability.

[0138] In the memory cards MC1 through MC6 described in FIGS. 1 through 6, their layout on the card substrate is set in order of the connector terminals 2, the controller chips 5 (5A and 5B) and the flash memory chips 4 with respect to one side of the card substrate. The connector terminals 2 are exposed from the casing 12. Each of the controller chips 5 (5A and 5B) has a shape long along the direction of the arrangement of the connector terminals 2 and includes a plurality of connector interface terminals 5Pi electrically connected to the connector terminals 2 through the connecting pads 3 on the connector terminal 2 side, and a plurality of memory interface terminals 5Pj electrically connected to the corresponding flash memory chip 4 on the flash memory chip 4 side. The flash memory chip 4 has a plurality of controller interface terminals 4Pk electrically connected to the controller chip 5 (5A, SB) on the controller chip 5 (SA, SB) side. The terminals 5Pi, 5P< highlight>j and 4Pk comprise, for example, bonding pads respectively.

[0139] According to the above, since the long controller chip 5 (SA, 5B) is caused to approach the connector terminals 2 and the flash memory chip 4 is placed on the side opposite to the controller chip 5 (5A, 5B), the area for laying out each flash memory chip 4 can be made relatively large. Further, wirings for respectively electrically connecting the connector terminals 2, the controller chip 5 (5A, 5B) and each memory chip 4 may be wired regularly in their arrangement directions. It is not necessary to adopt wirings which bypass each chip and are folded complicatedly.

[0140] The connecting pads 3 may be electrically connected to their corresponding connector interface terminals 5Pi of the controller chip 5 (5A, 5B) through bonding wires 7. Further, the memory interface terminals 5Pj of the controller chip 5 (5A, 5B) may be electrically connected to their corresponding controller interface terminals 4Pk of each flash memory chip 4 through bonding wires 8 and conductive patterns 9. Thus, this can simplify each wiring layer of the card substrate and is capable of contributing a cost reduction.

[0141] When interface terminals like bonding pads of a controller chip and a flash memory chip are placed in random orientations with respect to bonding pads 3 as shown in a comparative example of FIG. 14, wirings for respectively electrically connecting the connecting pads, the controller chip and the memory chip bypass the chips, pass complicated paths, complicate each wiring layer of the card substrate, degrade electrical characteristics, make an increase in cost and decrease reliability.

[0142] A detailed configuration of a state in which circuit elements are mounted on the multi media card-based memory card MC1 shown in FIG. 6 is illustrated in FIG. 15 by way of example on a plane basis. FIG. 16 is a vertical cross-sectional view of the configuration shown in FIG. 15. Test terminals 10 are not illustrated in the configurations shown in FIGS. 15 and 16. Further, FIGS. 15 and 16 include portions designated at reference numerals different from those shown in FIG. 6.

[0143] A card substrate 1 comprises a glass epoxy resin or the like. The connector terminals 2 are formed on the back of the card substrate 1 by conductive patterns. The controller chip 5 and the flash memory chips 4 are mounted on the surface of the card substrate 1 through wiring patterns and conductive patterns. In the drawing, reference numerals 3 respectively indicate connecting pads electrically connected to their corresponding connector terminals 2 via through holes 40.

[0144] Referring to FIG. 15, the bonding wires 8 shown in FIG. 6 are illustrated as 8a, 8b and 8c in parts. The controller chip 5 and the memory chips 4 are so-called bare chips, and the external terminals 5Pi, 5P< highlight>j and 4Pk thereof are bonding pads such as aluminum, an aluminum alloy, copper or a ferro-alloy or the like.

[0145] Each of the flash memory chips 4 has a memory cell array in which, for example, non-volatile memory cell transistors each having a control gate, a floating gate, and a source and drain are placed in matrix form. The flash memory chip 4 performs operations such as data reading, erasing, writing, verifying, etc. according to externally-supplied commands and addresses. The flash memory chip 4 includes, as plural external terminals 4Pk, an input terminal used for a chip enable signal (also called “chip select signal”)/CE for providing instructions for a chip selection, an input terminal used for a write enable signal/WE for providing instructions for a write operation, input/output terminals I/O0 through I/O7, an input terminal used for a command-data enable signal/CDE for providing instructions as to whether the input/output terminals I/O0 through I/O7 should be used for either the input/output of data or the input of addresses, an input terminal used for an output enable signal/OE for providing instructions for an output operation, an input terminal used for a clock signal/SC for providing instructions for data latch timing, an output terminal used for a ready/busy signal R/B for giving instructions as to whether the flash memory chip is being in a write operation, to the outside, and an input terminal used for a reset signal/RES.

[0146] The controller chip 5 controls the reading and writing of data from and into the flash memory chip 4 according to instructions given from outside. Further, the controller chip 5 has a security function for encrypting or encoding data to be written into the flash memory chip 4 in consideration of data security or copyright protection or the like and decrypting or decoding the data read from the flash memory chip 4.

[0147] The external terminals 5Pi of the controller chip 5 correspond to input/output functions of the connector terminals 2. An output terminal used for a chip select signal/CEO with respect to the flash memory chip 4, and an output terminal used for a chip select signal/CE1 with respect to the flash memory chip 4 are included as the external terminals 5Pj for obtaining memory access to the controller chip 5. Further, external terminals, which correspond to the external terminals 4Pk of the flash memory chip 4 and are reversed in input/output direction, are provided as the external terminals 5Pj.

[0148] As described above, the bonding wires 7 are used to connect the connecting pads 3 and their corresponding external terminals 5Pi of the controller chip 5, and the bonding wires 8a, 8b and 8c are used to connect the controller chip 5 and the flash memory chip 4. Thus, a large number of wiring patterns having the same functions as the connections thereof by the bonding wires may-not be formed on the card substrate 1 in a compact mass. Spaces lying above the controller chip 5 and each flash memory chip 4 can be utilized for wiring. In brief, substrate wiring can be simplified owing to air wiring of bonding wires. Accordingly, this can contribute to a reduction in the cost of the card substrate 1.

[0149] In the configuration shown in FIG. 15, the two flash memory chips 4 are parallel-connected to the controller chip 5 by the bonding wires. At this time, the two non-volatile memory chips 4 are mounted on the card substrate 1 in their position-shifted and overlapped state so that the external terminals 4Pk thereof are exposed. Thus, the distance to the controller chip 5 becomes short and routing lengths of the bonding wires 8b and 8c become short as compared with the case in which the non-volatile memory chips 4 are laid out without their overlapping. Accordingly, the possibility that undesired contacts and breaks of the bonding wires will occur, can be lessened. The amounts of shifts of a plurality of non-volatile memory chips at the time that they are stacked on one another, may be determined within a range in which one lower chip can exist below bonding external terminals of an upper chip. This is because when no lower chip exists below the bonding external terminals, there is a possibility that each chip will suffer damage due to a mechanical force at bonding.

[0150] Referring to FIG. 16, the controller chip 5 and non-volatile memory chips 4 are molded with a thermosetting resin 55 as a whole. At this time, each through hole 40 is not included in an area molded by the thermosetting resin 55. Thus, it is possible to eliminate the possibility that when they are molded under pressure, the mold resin 55 will leak into the reverse side of the card substrate 1 via each through hole 40, thereby causing a mold failure.

[0151] In FIG. 16, the casing 12 for covering the surface of the card substrate 1 can be made up of, for example, a metal cap or the like whose surface is subjected to insulating coating. Thus, as compared with a resin cap, it provides countermeasures against EMI (Electro Magnetic Interference) and also allows sealing based on mechanical fastening and high-temperature-based cap sealing.

[0152] Increasing the thickness of the controller chip 5 as compared with that of each flash memory chip 4 as described in FIG. 16 allows prevention of the occurrence of a failure in multi media card.

[0153] In FIG. 16, the thickness of the flash memory chip 4 is 220 μm and the thickness of the controller chip 5 is 280 μm. The height of the controller chip 5 after its mounting is 320 μm. A post-mounting height at the time that the two flash memory chips 4 are stacked and mounted, reaches 520 μm inclusive of the thickness of an adhesive layer for bonding their chip reverse sides to each other. Further, since the height of each bonding wire loop formed on the flash memory chips 4 and the controller chip 5 is about 200 μm, the whole height up to the uppermost portion of the bonding wire loop at the time that the two flash memory chips 4 are stacked, reaches 720 μm. Thus, the controller chip 5 is thicker than the flash memory chip 4. Further, the controller chip 5 is thinner than the thickness of the two flash memory chips 4. Alternatively, the post-mounting height of the controller chip 5 is about equal to or lower than the height of the two stacked and mounted flash memory chips 4.

[0154] It is thus necessary that in the memory card whose thickness is limited according to standards, when the chips are stacked on each other and mounted, the chips to be stacked are formed thin in advance to avoid failures such as the exposure of bonding wires on the mold resin 55. Increasing the thickness of the controller chip 5 as compared with that of the flash memory chip 4 in the memory card in which the flash memory chips 4 are placed in stacked form, yields the following effects.

[0155] A sufficient increase in the thickness of the controller chip 5 prevents failures such as cracking and chipping-off of the chip and also improves a handling characteristic at the time that each chip is placed on the substrate. Thus, even in the case of a memory card equipped with a large number of chips as in the case where the chips are placed in stacked form, a reduction in yield can be prevented from occurring and throughput in a mounting process can be improved.

[0156] Excessively thinning the thickness of the controller chip 5 yields an increase in the possibility that each chip will buckle due to pressure at the injection of a mold resin and an internal stress developed by curing and shrinkage at the time that the mold resin is cured. In the case of the flash memory chips 4 placed in stacked form as compared with it, a sufficient strength can be obtained even in the case of a thin chip because they are stacked, and buckling can be avoided. Thus, a chip placed in a single layer needs to increase its thickness as compared with that of chips mounted in stacked form with a view toward obtaining a strength equivalent to such an extent as to be capable of avoiding the buckling.

[0157] The controller chip 5 is mounted to a portion nearer the connector terminals 2 as compared with the flash memory chips 4. In the case of the portion nearer each connector terminal 2, distortion is developed in the memory card due to a stress given or suffered from the socket terminal 22 connected to the connector terminals 2 when the memory card is in use. Such distortion is transferred to the controller chip 5 nearer the connector terminals 2 as a large internal stress. As a result of the repeated use of the memory card, there is a possibility that a failure such as the generation of chip's cracking will occur. However, if a structure or configuration is adopted wherein the chip mounted onto the portion nearer the connector terminals 2 is set thicker than each chip mounted to a portion far from the connector terminals 2, then resistance to the stress suffered from the connector terminals 2 can be sufficiently ensured and a failure such as breakage developed inside the memory card due to its repeated use can be avoided.

[0158] The card substrates 1, and 1A through 1E are respectively provided with the test terminals 10 connected to the controller chip 5 and the memory chips 4 in order to efficiently test the post-mounting controller chip 5 and flash memory chips 4. Since the test terminals 10 may be avoided from being always exposed after they have been incorporated into a casing, the test terminals are formed on a surface on the side opposite to a forming surface of the connector terminals 3 of the card substrate from this point of view.

[0159] The state of connections of the test terminals of the multi media card-based memory card MC1 shown in FIG. 6 is illustrated in FIG. 17 by way of example. In FIG. 17, the state of connections between a controller chip 5 and each non-volatile memory chip 4 is simplified in the drawing to put emphasis on the state of connections of the test terminals. In FIG. 17, circuit elements each having the same function as FIG. 6 are identified by the same reference numerals and their detailed description will therefore be omitted.

[0160] The controller chip 5 has an input terminal (also described simply “test terminal/TEST”) for a test signal/TEST pulled up thereinside as one of external terminals 5Pj although it is not shown in FIG. 6. When a low level is inputted to the test terminal/TEST, the test terminal/TEST serves so as to control a terminal for interface with each non-volatile memory chip 4, particularly, an output terminal and an input/output terminal to a high-output impedance state or an input/output inoperable or not-ready state. Further, a TEST input terminal may be input-controlled according to a serial command (encrypted or encoded command) for security.

[0161] A test control terminal 10a connected to the test terminal/