DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] The preferred embodiments in accordance with the present invention will be described in detail based on the accompanying drawings. Here, in all the drawings for describing the preferred embodiments, members having like functions are designated by like reference characters and their descriptions will not be repeated.

First Embodiment

[0032] FIG. 1 is a plan view showing an example of the structure of a semiconductor device (T-TFBGA) in accordance with a first embodiment of the present invention. FIG. 2 is a bottom view showing the structure of the semiconductor device shown in FIG. 1 . FIG. 3 is a sectional view showing the structure of the cross section taken along the line A-A in FIG. 2 . FIG. 4 is a plan view showing an example of a lead pattern in a tape substrate of the semiconductor device shown in FIG. 1 . FIG. 5 is a partial enlarged plan view showing the detailed structure of a portion B in FIG. 4 . FIG. 6 is a process flowchart showing an example of the manufacturing procedures of a semiconductor device in accordance with the first embodiment of the present invention. FIG. 7 is a partial side view showing an example of a packaging embodiment of a semiconductor device in accordance with the first embodiment of the present invention. FIG. 8 is a partial plan view showing an example of a packaging embodiment of a semiconductor device in accordance with the first embodiment of the present invention.

[0033] The semiconductor device in accordance with the first embodiment shown in FIGS. 1 to 3 is a semiconductor package of a fine-pitch type having a relatively large number of pins for its chip size such as a microcomputer, an ASIC (Application Specific Integrated Circuit) or the like, and is a T-TFBGA 8 of a Fan-Out and thin type using a tape substrate 2 and having a plurality of solder balls 3 , which are external terminals, on the outside of a semiconductor chip 1 .

[0034] The constitution of the T-TFBGA 8 will be explained by the use of FIGS. 1 to 5 . The T-TFBGA 8 comprises a tape substrate 2 provided with a plurality of leads 2 a for supporting the semiconductor chip 1 and corresponding to pads (surface electrodes) 1 a of the semiconductor chip 1 and connected thereto; and dummy leads 2 e arranged in the corner portions such that the leads 2 a are symmetrically arranged with respect to a diagonal line 5 ; gold bumps 7 which are conductive members for connecting the pads 1 a of the semiconductor chip 1 to the leads 2 of the tape substrate 2 ; a frame-shaped reinforcing member 4 for reinforcing the tape substrate and attached to a back face 2 c which is a face opposite to the external terminal mounting face 2 b of the tape substrate 2 on which solder balls 3 are mounted; and a plurality of solder balls 3 , which are external terminals, attached to the external terminal mounting face 2 b of the tape substrate 2 and arranged on the outside periphery of the semiconductor chip 1 , wherein the dummy leads 2 e disperse the stress (for example, thermal stress) applied to the corner portions of the tape substrate 2 to the whole regions of the corner portions.

[0035] The tape substrate 2 of the T-TFBGA 8 in accordance with the first embodiment is shaped like a square in a plan view, as shown in FIG. 4 , and has a plurality of leads 2 a , which are wirings and which are formed by placing a copper foil on a film base material 2 f formed of a polyimide tape, as shown in FIG. 3 .

[0036] In the center of the tape substrate 2 , as shown in FIG. 4 , is formed a square opening 2 h in which the semiconductor chip 1 can be arranged, and one ends of the plurality of leads 2 a are projected and are connected to the corresponding pads 1 a of the semiconductor chip 1 via the gold bumps 7 .

[0037] Thus, the semiconductor chip 1 is supported by the one ends of the plurality of leads 2 a of the tape substrate 2 via the gold bumps 7 .

[0038] Further, as shown in FIG. 4 , the other ends of the respective leads 2 a are connected to the ball lands 2 i which are terminals on which the solder balls 3 are mounted. Therefore, the ball lands 2 i corresponding to the number of external terminals (number of pins) are arranged in an uncovered state on the external terminal mounting face 2 b of the tape substrate 2 .

[0039] As shown in FIG. 3, a solder resist 2 d which is an insulating film for protecting and insulating the respective leads 2 a are formed on the surface of the external terminal mounting face 2 b of the tape substrate 2 . Here, though the solder resist 2 d covering the respective leads 2 a is omitted in FIG. 4 and FIG. 5 in order to clearly illustrate the lead pattern of the external terminal mounting face 2 b , the surface of the external terminal mounting face 2 b of the tape substrate 2 except for the respective ball lands 2 i is covered with the solder resist 2 d , as shown in FIG. 3 .

[0040] Though the number of ball lands 2 i shown in FIG. 4 is smaller than that of the solder balls 3 shown in FIG. 2 in order to clearly illustrate the lead pattern, the number of the ball lands 2 i shown in FIG. 4 is essentially equal to the number of the solder balls 3 shown in FIG. 2 .

[0041] In the T-TFBGA 8 of the first embodiment, as shown in FIG. 5 , the dummy leads 2 e are mounted in the vicinity of the corner portions of the tape substrate 2 such that the lead pattern formed by the wiring of the leads 2 a is symmetrically arranged with respect to the diagonal lines 5 of the external terminal mounting face 2 b of the tape substrate 2 .

[0042] Therefore, the lead pattern including the leads 2 a and the dummy leads 2 e are symmetrically arranged with respect to the diagonal lines 5 of the tape substrate 2 because the dummy leads 2 e are formed near the corner portions of the tape substrate 2 . As a result, when a thermal stress is applied to the portions near the corner portions of the tape substrate 2 in a temperature cycle test or the like, the thermal stress results in being dispersedly applied to the whole areas near the corner portions of the tape substrate 2 .

[0043] The dummy leads 2 e are formed at all the four corner portions of the tape substrate 2 in the T-TFBGA 8 of the first embodiment, as shown in FIG. 4 .

[0044] Further, though the leads 2 a are illustrated by the solid lines and the dummy leads 2 e are illustrated by the dotted lines in FIG. 4 and FIG. 5 in order to make a distinction between the leads 2 a and the dummy leads 2 e , the actual dummy leads 2 e are long thin wirings like the leads 2 a (ditto for FIG. 9 and FIG. 10 of a second embodiment described below).

[0045] The dummy leads 2 e are formed in the same manufacturing process by using a copper foil or the like as is the case with the respective leads 2 a . However, both ends of the respective dummy leads 2 e are terminated without being connected to the pads 1 and the ball lands 2 i of the semiconductor chip 1 and hence do not have the function of transmitting an electric signal.

[0046] Therefore, it is desirable that the one ends of semiconductor chip side of the dummy leads 2 e are not projected into the opening 2 h of the tape substrate 2 .

[0047] Also, the reinforcing member 4 mounted on the back face 2 c of the tape substrate 2 , as shown in FIG. 3 , reinforces the solder ball mounting portions of the tape substrate 2 to enhance its strength so as to improve the flatness of the T-TFBGA 8 , so that the reinforcing member 4 is shaped like a frame as shown in FIG. 1 .

[0048] Therefore, the reinforcing member 4 is preferably formed of a metal thin plate in order to enhance the strength of the above-mentioned solder ball mounting portions of the tape substrate 2 and, for example, when the T-TFBGA 8 is mounted on a packaging substrate 9 shown in FIG. 7 , in order to bring the thermal expansion coefficients of both (packaging substrate 9 and T-TFBGA 8 ) close to each other, the reinforcing member 4 is preferably formed of a metal thin plate (a thin plate of copper alloy) formed by plating a copper foil with nickel, but it may be formed of the other materials.

[0049] This brings the thermal coefficient of the T-TFBGA 8 and that of the packaging substrate 9 close to each other and when the T-TFBGA 8 is mounted on the packaging substrate 9 , this can reduce the stress applied to the solder balls 3 connected to both and thus can improve reliability in connection of the solder balls 3 .

[0050] The gold bumps 7 formed on the pads 1 a of the semiconductor chip 1 , as shown in FIG. 3 , are formed, for example, by growing gold plating on the pads 1 a after a semiconductor integrated circuit is formed in a semiconductor wafer before it is diced, and are terminals for connecting the pads 1 a of the semiconductor chip 1 to the leads 2 a of the tape substrate 2 .

[0051] Around the junctions where the semiconductor chip 1 and the leads 2 a are bonded to each other via the gold bumps 7 are formed a sealing portion 6 for covering them.

[0052] The sealing part 6 is formed, for example, by sealing the semiconductor chip 1 and the projecting portions of the leads 2 a with an epoxy-based thermosetting resin for sealing and is formed by potting in the case of the T-TFBGA 8 of the first embodiment.

[0053] The sealing part 6 , however, is not formed by potting, but may be formed by molding.

[0054] The solder balls 3 , which are external terminals, mounted on the T-TFGBA 8 are ball-shaped terminals having a diameter of about 0.3 mm, for example, and are further mounted on the respective ball lands 2 i of the external terminal mounting face 2 b of the tape substrate 2 at narrow pitches because the T-TFBGA 8 is a fine-pitch type.

[0055] In FIG. 7 and FIG. 8 will be shown a packaging embodiment in which the T-TFBGA 8 is packaged on a packaging substrate 9 . The T-TFBGA 8 can be packaged on the same packaging substrate 9 with a semiconductor device of the other surface packaging type such as a QFP (Quad Flat Package) 10 and the like. Also when it is packaged, it can be packaged with the QFP 10 in the same solder reflow process that is the packaging process of the QFP 10 . In other words, the T-TFBGA 8 can be packaged mixedly with the QFP 10 or the like.

[0056] Next, the manufacturing method of the semiconductor (T-TFBGA 8 ) of the first embodiment will be described according to a manufacturing process flowchart shown in FIG. 6 .

[0057] Here, in the first embodiment will be described a case where individual T-TFBGAs 8 are manufactures by using a long multiple film tape capable of manufacturing a plurality of T-TFBGAs 8 .

[0058] To begin with, a semiconductor wafer (not shown) is prepared which is mounted with a plurality of semiconductor chips 1 each of which has a desired semiconductor integrated circuit formed on its main surface 1 b.

[0059] Further, gold bumps 7 (conductive parts) are formed by gold plating on the pads 1 a of the respective semiconductor chips 1 on the semiconductor wafer, with predetermined regions covered with a mask, in the above-mentioned state of the semiconductor wafer.

[0060] Then, this semiconductor wafer is diced and separated into individual semiconductor chips 1 , and then the individual semiconductor chips 1 are subjected to a predetermined test, and the semiconductor chips 1 which are judged as being good ones are prepared.

[0061] On the other hand, a tape substrate 2 is prepared for the respective T-TFBGAs 8 , said tape substrate having leads 2 a , which are wirings to be connected to the corresponding pads 1 a of the semiconductor chip 1 , and the dummy leads 2 e formed in the corner portions such that the leads 2 a are symmetrically arranged with respect to the diagonals 5 (step S 1 ).

[0062] Here, a multiple film tape of a polyimide film or the like in which a plurality of tape substrates 2 are connected to each other is prepared.

[0063] As a manufacturing procedure of the tape substrate 2 , first, a copper foil is placed on the external terminal mounting face 2 b side of the film base material 2 f , which is the above-mentioned film tape, by the use of an epoxy-based adhesive or the like, and thereafter the copper foil layer is subjected to an etching process to make a predetermined shape, whereby the leads 2 a and the dummy leads 2 e are formed.

[0064] Thereafter, at step S 2 , a reinforcing member 4 shaped like a frame is placed on the outer peripheral portion of the back face 2 c of the tape substrate 2 .

[0065] Then, an inner lead binding process is performed at step S 3 .

[0066] Here, the gold bumps 7 formed on the pads 1 a of the semiconductor chip 1 are bonded to the corresponding leads 2 a by a gang bonding, that is, a collective bonding.

[0067] When they are bonded to each other, first, the semiconductor chip 1 is arranged at the opening 2 h in the center of the tape substrate 2 and the one ends of the leads 2 a arranged at the opening 2 h are thermally pressed and bonded to the pads 1 a of the semiconductor chip 1 via the gold bumps 7 , whereby the pads 1 a of he semiconductor chip 1 are bonded to the corresponding leads 2 a of the tape substrate 2 via the gold bumps 7 and the semiconductor chip 1 is supported by the opening 2 h of the tape substrate 2 by means of the leads 2 a.

[0068] In other words, in the inner lead bonding process at step S 3 , a chip mounting process and a bonding process for bonding the leads 2 a of the tape substrate 2 to the pads 1 a of the semiconductor chip 1 are performed at the same time.

[0069] Thereafter, the semiconductor chip 1 , the leads 2 a , and the gold bumps 7 are sealed by potting by the use of an epoxy-based thermosetting sealing resin to form a sealing part 6 (step S 4 ).

[0070] The sealing part 6 may be molded by the use of the above-mentioned sealing resin.

[0071] Then, at step S 5 , a plurality (a predetermined number) of solder balls 3 , which are external terminals, are mounted on the outer periphery of the semiconductor chip 1 in the external terminal mounting face 2 b of the tape substrate 2 .

[0072] When the solder balls 3 are mounted, first, the solder balls 3 are provisionally fixed to the ball lands 2 i of the tape substrate 2 by the use of flux and then are passed through a reflow furnace having a peak temperature of about 230° C., for example, to fix the solder balls 3 .

[0073] Thereafter, at step 6 , individual tape substrates 2 , that is, individual T-TFBGAs 8 are diced and separated from the multiple film tape and this is the end of the manufacturing process of the individual T-TFBGAs 8 (step S 7 ).

[0074] Further, when the T-TFBGA 8 of the first embodiment is packaged on a packaging substrate 9 or the like, it can be packaged on the same packaging substrate 9 with the semiconductor device of the other surface packaging type such as the QFP 10 or the like, as shown in FIG. 7 and FIG. 8 .

[0075] In that case, the T-TFBGA 8 can be packaged by the same solder reflow process that is the packaging process of the QFP 10 , that is, can be packaged mixedly with the QFP 10 or the like.

[0076] According to the semiconductor device (T-TFBGA 8 ) of the first embodiment and its manufacturing method, the following operation and effects can be obtained.

[0077] Namely, since the dummy leads 2 e are formed in the corner portions of the tape substrate 2 of the T-TFBGA 8 such that the lead pattern of the leads 2 a is symmetrically arranged with the diagonal lines 5 of the tape substrate 2 , when stress such as a thermal stress or the like is applied to the corner portions of the tape substrate 2 in a temperature cycle test, this stress applied to the corner portions can be dispersed nearly uniformly to both sides of the diagonal lines 5 of the tape substrate 2 .

[0078] This can prevent the stress form concentrating on the specific regions in the corner portions of the tape substrate 2 in the temperature cycle test and can prevent a break in the leads 2 a near the corner portions of the tape substrate 2 .

[0079] As a result, this can improve the reliability of the semiconductor device of the Fan-Out type using the tape substrate 2 , that is, the T-TFBGA 8 .

Second Embodiment

[0080] FIG. 9 is a plan view showing an example of a lead pattern in the tape substrate of a semiconductor device of a second embodiment in accordance with the present invention. FIG. 10 is a partial enlarged plan view showing the detailed structure of a portion C in FIG. 9 .

[0081] The semiconductor device of the second embodiment is a T-TFBGA 11 of the same Fan-Out type as is the type of the first embodiment and is different from the T-TFBGA 8 of the first embodiment in that dummy leads 2 e are mounted in the vacant regions 2 g where the leads 2 a of the tape substrate 2 are not mounted, as shown in FIG. 9 and FIG. 10 .

[0082] In other words, since the leads 2 a are not mounted in the corner portions of the tape substrate 2 and the dummy leads 2 e are mounted in the vacant regions 2 g of the corner portions such that the leads 2 a and the dummy leads 2 e are arranged in good balance, the stress applied to the corner portions are dispersed to the whole areas of the corner portions and the strength of the corner portions in the tape substrate 2 is enhanced.

[0083] The other constitution of the T-TFBGA 11 of the second embodiment is the same as that of the T-TFBGA 8 described in the first embodiment and its description will not be repeated.

[0084] As for the manufacturing method of the T-TFBGA 11 of the second embodiment, the T-TFBGA 11 of the second embodiment can be manufactured by the same manufacturing method as is used for manufacturing the T-TFBGA 8 of the first embodiment by the use of a tape substrate 2 having dummy leads 2 e in the vacant regions 2 g in the corner portions where leads 2 a , as shown in FIG. 9 , are not mounted.

[0085] Further, as for the packaging of the T-TFBGA 11 , the T-TFBGA 11 can be mixedly packaged by the same solder reflow packaging process that is used for packaging the semiconductor device of the other surface packaging type (for example, the QFP 10 shown in FIG. 7 and FIG. 8 ) as is the case with the T-TFBGA 8 of the first embodiment.

[0086] According to the T-TFBGA 11 of the second embodiment, since the dummy leads 2 e are formed in the vacant regions 2 g in the corner portions in the tape substrate 2 where leads 2 a are not formed, the strength of the corner portions of the tape substrate 2 can be enhanced. As a result, this can prevent a break in the leads 2 a in the corner portions of the tape substrate 2 in the temperature cycle test.

[0087] This can improve the reliability of the T-TFBGA 11 of the Fan-Out type.

[0088] Also, since the strength of the corner portions of the tape substrate 2 can be enhanced, the tape substrate 2 can be prevented from being warped or deformed and therefore the flatness of the tape substrate 2 in the T-TFBGA 11 can be improved.

[0089] Therefore, the packaging performance of the T-TFBGA 11 can be improved.

[0090] Also, since the dummy leads 2 e are formed in the vacant regions 2 g in the corner portions of the tape substrate 2 where the leads 2 a are not formed, it is possible to disperse stress such as thermal stress and the like to the whole area of the corner portions of the tape substrate 2 , said stress being applied to the corner portions of the tape substrate 2 during the temperature cycle test or the like.

[0091] This can prevent the stress from being concentrated on the vacant regions 2 g in the corner portions of the tape substrate 2 where the leads 2 a are not formed and hence can prevent a break in the leads 2 a formed near the vacant regions 2 g . As a result, this can improve the reliability of the T-TFBGA 11 .

Preferred Embodiment 3

[0092] FIG. 11 is a plan view showing an example of the structure of a semiconductor device in accordance with a third embodiment of the present invention. FIG. 12 is a bottom view showing the structure of the semiconductor device shown in FIG. 11 . FIG. 13 is a sectional view showing the structure of the cross section taken along the line A-A in FIG. 12 . FIG. 14 is a partial enlarged plan view showing an example of a lead pattern of the tape substrate of the semiconductor device shown in FIG. 11 to FIG. 13 .

[0093] The semiconductor device of the third embodiment is a T-HBGA (Tape-type Heat-sink BGA) or T-HFBGA (Tape-type Heat-sink Fine-pitch BGA), which is one kind of T-FBGA or T-TFBGA described in the first embodiment or the second embodiment. The semiconductor device of the third embodiment is a semiconductor package of a fine-pitch type having many pins for the size of a chip such as a microcomputer, an ASIC, or the like, and has 300 pins or more, for example, 352 pins, 400 pins or 600 pins.

[0094] As shown in FIG. 11 and FIG. 13 , the semiconductor device 13 of the third embodiment has a tape substrate 2 , which is square in a plan view and which has a square opening for arranging a semiconductor chip 1 in its center; and a reinforcing member 4 which is mounted on the back face 2 c of the tape substrate 2 and which covers the back face of the semiconductor chip 1 from above the back face 2 c . As shown in FIG. 12 and FIG. 13, a plurality of rows of solder balls 3 are mounted on the external terminal mounting face 2 b of the tape substrate 2 such that they surround the semiconductor chip 1 as is the case with the first embodiment. The semiconductor chip 1 is covered with a sealing portion 6 formed of resin. Further, a solder resist 2 d is formed on the surface of the external terminal mounting face 2 b of the square tape substrate 2 except for the solder balls 3 and the ball lands 2 i under the solder balls 3 . In other words, the leads 2 a are covered with the solder resist 2 d.

[0095] As shown in FIG. 14 , the dummy leads 2 e are formed in and in the vicinity of the corner portions of the external terminal mounting face 2 b of the tape substrate 2 such that a lead pattern is symmetrically arranged with respect to the diagonal line 5 of the tape substrate 2 . The one ends of the dummy leads 2 e are terminated on the tape substrate 2 without projecting into the opening 2 h of the tape substrate 2 and the other ends are terminated without being bonded to the ball lands 2 i.

[0096] In this way, the lead pattern composed of the leads 2 a and the dummy leads 2 e is symmetrically arranged with respect to the diagonal lines 5 of the tape substrate 2 in the external terminal mounting face 2 b side and hence the thermal stress generated when a temperature cycle test is conducted or the semiconductor device is packaged on a wiring board is not applied intensively to the corner portions and their vicinities of the tape substrate but it is dispersed to the corner portions and their vicinities. As a result, this can prevent a break in the leads 2 a formed in the corner portions and their vicinities of the tape substrate 2 and can improve the reliability of the T-HBGA.

[0097] Further, the semiconductor device of the third embodiment has slits 12 in some portions of the reinforcing member 4 , as shown in FIG. 11 . These slits 12 prevent the problems that air or gas in the region surrounded by the tape substrate 2 , the reinforcing member 4 , and the semiconductor chip 1 is expanded to separate the reinforcing member 4 from the tape substrate 2 or to break the leads 2 a of the tape substrate 2 ; that is, these slits 12 are openings for relieving the gas.

Preferred Embodiment 4

[0098] FIG. 15 is a partial enlarged plan view showing an example of a lead pattern in a tape substrate of a semiconductor device in accordance with a fourth embodiment of the present invention.

[0099] The semiconductor device 14 of the fourth embodiment is the same T-HBGA or T-HFBGA as the third embodiment and is different from the third embodiment in that a plurality of dummy leads 2 e are formed in the vacant regions 2 g in the corner portions and their vicinities of the external terminal mounting face 2 b of the tape substrate 2 where the leads 2 a are not formed, as shown in FIG. 15 . The plurality of dummy leads 2 e are symmetrically arranged with respect to the diagonal lines 5 of the tape substrate 2 and are formed also along the diagonal lines 5 .

[0100] In this way, since the dummy leads 2 e are formed in the vacant regions 2 g where the leads 2 a are not formed, a lead pattern including the dummy leads 2 e and the leads 2 a are arranged in good balance with respect to the diagonal lines 5 in the corner portions and their vicinities of the external terminal mounting face 2 b side of the tape substrate 2 , which can improve the strength of the corner portions and their vicinities of the tape substrate 2 .

[0101] As a result, this can disperse the thermal stress generated when the temperature cycle test is conducted or the semiconductor device is packaged on the wiring board by reflow soldering or the like to the whole area of the corner portions and their vicinities and hence can prevent a break in leads 2 a.

[0102] In this connection, in the fourth embodiment, if the lead pattern is arranged in good balance with respect to the diagonal lines 5 of the tape substrate 2 , the dummy leads 2 e are not necessarily formed along the diagonal lines 5 . However, if the dummy leads 2 e are formed along the diagonal lines 5 , they can further enhance the strength of the corner portions and their vicinities of the tape substrate 2 as compared with the case where the dummy leads 2 e are not formed along the diagonal lines 5 .

[0103] Up to this point, while the invention made by the present inventors have been described based on the first, second, third and fourth embodiments, it is not intended to limit the present invention to the first, second, third and fourth embodiments. On the contrary, needless to say, the present invention may be further modified within the spirit and scope of the present invention as defined by the appended claims.

[0104] For example, while the case where the tape substrate 2 is prepared and then the reinforcing member 4 is mounted before the inner lead bonding process has been described in the manufacturing method of the semiconductor device (T-TFBGA 8 , 11 ) in the first and second embodiments, as for the mounting procedure of the reinforcing member 4 , the reinforcing member 4 may be mounted between the resin sealing process and the solder ball mounting process, or the semiconductor device may be delivered (prepared) by using the tape substrate 2 on which the reinforcing member 4 is previously mounted.

[0105] Also, while the case where individual semiconductor devices are manufactured by using a long multiple film tape including a plurality of tape substrates 2 linked to each other has been described in the first and second embodiments, the individual semiconductor device may be manufactured by using the tape substrate 2 which is previously cut as an individual semiconductor.

[0106] Also, while the case where the dummy leads 2 e are formed in all the four corner portions of the tape substrate 2 has been described in the first, second, third and fourth embodiments, the dummy leads 2 e are not necessarily formed in all the corner portions of the tape substrate 2 .

[0107] However, in the tape substrate 2 if a corner has a vacant space where the leads 2 a can be formed, the dummy leads 2 e needs to be formed therein. As a result, it is essential only that the leads 2 a or the dummy leads 2 e are formed so as to eliminate the vacant space in all the corner portions of the tape substrate 2 .

[0108] This can disperse stress in all the corner portions of the tape substrate 2 .

[0109] Also, the method of arranging the dummy leads 2 e in the corner portions of the tape substrate 2 may be a combination of the methods described in the first, second, third and fourth embodiments.

[0110] In other words, in the corner portions of the tape substrate 2 , the dummy leads 2 e are formed such that the leads 2 a are symmetrically arranged with respect to the diagonal lines 5 of the tape substrate 2 and further the dummy leads 2 e are formed also in the vacant regions 2 g in the corner portions as shown in FIG. 9 and FIG. 10 . In this case, the result is that the dummy leads 2 e are formed in all the vacant regions 2 g of the corner portions of the tape substrate 2 and the leads 2 a are arranged symmetrically with respect to the diagonal lines 5 .

[0111] This can enhance the strength of the corner portions of the tape substrate 2 and can disperse the stress applied to the corner portions of the tape substrate 2 to the whole area of the corner portions.

[0112] Also, while the case where the semiconductor device is the T-TFBGA 8 or 11 of the fine-pitch type and the Fan-Out type has been described in the first and second embodiments, it is essential only that the semiconductor device is formed of the tape substrate 2 and has the external terminals at least on the outside periphery of the semiconductor chip 1 , and then the semiconductor device is not necessarily a semiconductor device of the Fan-Out type but it may be a semiconductor device of the Fan-In/Out type and further may be the other semiconductor device such as T-TBGA, LGA (Land Grid Array) or the like.

[0113] The advantages produced by the typical invention among the inventions disclosed in the present application will be described in brief as follows.

[0114] (1) According to the present invention, in the tape substrate of a semiconductor device, since dummy leads are formed in the corner portions such that leads are symmetrically arranged with respect to the diagonal lines of the tape substrate, the stress applied to the corner portions of the tape substrate can nearly uniformly dispersed to both sides with respect to the diagonal lines. This can prevent a break in the leads in the corner portions of the tape substrate. As a result, this can improve the reliability of the semiconductor device.

[0115] (2) According to the present invention, in the tape substrate of a semiconductor device, since dummy leads are formed in the vacant regions of the corner portions where leads are not formed, they can enhance the strength of the corner portions of the tape substrate. This can prevent a break in the leads in the corner portions of the tape substrate. As a result, this can improve the reliability of the semiconductor device.

[0116] (3) According to the above (2), since the strength of the corner portions of the tape substrate can be enhanced, the tape substrate can be prevented from being warped or deformed. This can improve the flatness of the tape substrate. Therefore, this can improve the performance of packaging the semiconductor device.