DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0026] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. Preferred embodiments of methods/apparatus according to the present invention are based on a process transferring data or S/W programs, which are to be down-loaded onto processors, by using a multiplexing mode. The multiplexing mode down-load is preferably characterized by a single access of a specific memory where the S/W programs or the data are loaded, creating the accessed information in a preferably pre-defined information processing code (IPC) format, and transferring the S/W programs or the data having the same contents to a plurality of processors to be reset through a single-transfer manner or operation. The single-transfer operation, in general, signifies that the plurality of processors and addresses of the processors as well as the representative address of the processors are pre-defined suitable for the IPC format so that messages can be delivered to the plurality of processors through only a single-transfer operation by using the IPC format.

[0027] FIG. 3 is a diagram illustrating a preferred embodiment of a method for grouping lower processors with identical group address by using a representative address, which is used for down-loading S/W programs or data onto the plurality of lower processors from an upper processor at the same time according to preferred embodiments of the present invention. The plurality of processors have their own prescribed address of 4 bytes. The prescribed address of the plurality of processors preferably includes four elements, each being 1 byte in length. Among the respective elements, a node address (NA) of 1 byte represents a process element ID, a BHIU address (BA) of 1 byte represents a processor ID, a cinu address (CA) of 1 byte represents a network group ID 1 , and a slot address (SA) of 1 byte represents a network group ID 2 .

[0028] For example, assume respective processor information that includes the above elements is the following: NA: 0 /BA: 1 /CA 2 /SA 2 in case of an A processor; NA: 3 /BA: 4 /CA 1 /SA 2 in case of a B processor; NA: 0 /BA: 6 /CA 2 /SA 2 in case of a C processor; and NA: 0 /BA: 1 /CA 1 /SA 2 in case of a D processor of a plurality of lower processors. In this example, the method for grouping the representative address is preferably performed with the CA information and the SA information.

[0029] Thus, according to the above processor information, the processors A and C are grouped by an identical group address (e.g., CA 2 ), while the processors B and D are grouped by a different identical group address (e.g., CA 1 ).

[0030] To be specific, the representative address grouping the processors A and C is determined to be NAFE BAFF CA 2 SA 2 , whereas the representative address grouping the processors B and D is determined to be NAFF BAFF CA 1 SA 2 . In a similar manner described above, according to the preferred embodiments, the grouping can be performed with both the CA information and the SA information, just the CA information or just the SA information.

[0031] FIG. 4 is a flow chart illustrating a preferred embodiments of a method for down-loading programs or data in a process of resetting processors in a mobile communication switching system. As shown in FIG. 4 , the preferred embodiments of the method for down-loading the S/W programs or the data from an upper processor onto a plurality of lower processors in the process of resetting the processors in the mobile communication switching system preferably starts in step S 1 , where a lower processor requests the upper processor for an information down-load. From step S 1 , control continues to step S 2 where the upper processor accesses once a memory containing the data to be transferred to the lower processor. From step S 2 , control continues to step S 3 , where it is determined whether the single memory access has an error. If the determination in step S 3 is an error was detected, control returns to step S 1 .

[0032] If the determination in step S 3 is no error, control continues to step S 4 where the grouping is conducted according to the representative address preferably according to the defined processor address as shown in FIG. 3 . From step S 4 , control continues to step S 5 where a message is created preferably in the pre-defined IPC data format.

[0033] From step S 5 , control continues to step S 6 where the representative address grouping the lower processors are injected into the message created in the pre-defined IPC data format, which is transferred to a pertinent address for a multiplexing mode down-load. The plurality of processors within the grouped address, which generally receive messages transmitted to the grouped representative address, receive the transmitted IPC format message so as to down-load the programs or the data. Thus, in step S 7 , the plurality of processors can down-load the programs or the data at the same time, which reduces a required time for resetting the processors in a mobile communication switching system. Further, additional system changes are not incurred.

[0034] The representative address grouping the lower processors are injected into the created message, which is transferred to a pertinent address for the multiplexing mode down-load in step S 6 . The method for the multiplex mode downloading the programs or the data of the same contents onto the plurality of lower processors preferably includes the steps of grouping the plurality of lower processors to be down-loaded with the same group address, converting the message to be transferred to the representative address into the IPC format when down-loading the S/W programs or the data from the upper processor onto the lower processor then transferring the converted message, and receiving the IPC format message transmitted from the upper processor by the plurality of lower processors within the same group so as to down-load the programs or the data. Accordingly, transfer the S/W programs or the data of the same contents to the plurality of processors through a once-transfer manner.

[0035] As shown in FIG. 4 , the multiplexing mode down-load is used in the mobile communication switching system to group the plurality of processors with the same group address. For example, if an upper processor CCP is requested for a down-load from 15 pertinent lower processor 15 SVCs, the CCP accesses once a specific memory containing programs to be down-loaded onto the pertinent SVCs, and converts the contents of the memory into the pre-defined IPC format. Here, the representative address of the grouped SVCs is set to be transferred. The plurality of SVCs, namely lower processors, simultaneously receive the down-loaded programs and then concurrently start up.

[0036] As described above, the preferred embodiments of methods for down-loading the programs or the data having the same contents onto the plurality of lower processors can include grouping the plurality of lower processors using a representative address to be down-loaded with the same group address, converting the message to be transferred to the representative address into the IPC format when down-loading the S/W programs or the data from the upper processor onto the lower processor, transferring the converted message and receiving the IPC format message, which was transmitted from the upper processor, by the plurality of lower processors within the same group so as to all down-load the programs or the data.

[0037] As described above, preferred embodiments of methods for down-loading S/W programs or data from a first processor to a plurality of additional processors according to the present invention have various advantages. The first processor performs a single access for the down-loaded S/W programs or the data. Accordingly, a process time is reduced. Each of the additional processors do not perform a specific request of the first processor for the down-loaded S/W programs or the data. The plurality of additional processors can each directly start operating the same down-loaded S/W program or data. Accordingly, a time for resetting processors in a mobile communications switching system can be reduced or minimized without altering a prescribed information processing code (IPC) format using the preferred embodiments.

[0038] The foregoing embodiments and advantages are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures.