DETAILED DESCRIPTION OF THE PRESENT INVENTION

[0045] Applicant believes that a significant source of the breakdown of the cell is charge trapped far from the relevant drain junction, which charge is hard to erase. This is shown in FIGS. 3A, 3B , 3 C and 3 D, to which reference is now made.

[0046] FIGS. 3 show the charge stored in right area 108 of the nitride layer as a function of distance along the channel for one cell. FIG. 3A shows that, after the first cycle of programming, a significant amount of charge, labeled 80 , is stored close to the right bit line, which is the drain for programming and erasure. As one moves away from the drain, the amount of charge reduces, eventually to zero. FIG. 3B shows the amount of charge, labeled 82 , left after the first erase cycle. The erase electric field is typically so effective that it removes extra electrons (more than were present in charge 80 ) such that section 82 is positive while section 80 is negative. Section 82 is thus, hatched, to indicate that it is positively charged.

[0047] FIGS. 3C and 3D parallel FIGS. 3A and 3B , respectively, but for after 20,000 cycles. After programming, there is a significant charge, labeled 84 , close to the drain, as in FIG. 3A . However, there is also another section of charge, labeled 86 , further from the drain, which diffused there over time and was not erased during from previous erase cycles. After the 20,000 ^th erase cycle, the extra section 86 still remains and is negatively charged, though the previously programmed section 84 has become positively charged section 88 .

[0048] As can be understood from the above discussion, the diffused charge, in section 86 , is not erased during erasure operations and remains trapped there. Trapped charge 86 acts as partially programmed charge. It is due to trapped charge 86 that the fewer and fewer programming pulses are required to achieve the programmed threshold voltage level (since the bit is already, in effect, partially programmed) and that more and more erasure pulses are required to achieve the erase threshold voltage level (since trapped charge 86 is not removed).

[0049] Furthermore, the trapped charge 86 effects the reverse read (curves 60 and 64 of FIG. 2A ) but not the forward read (curves 62 and 66 ), which is why the two sets of curves are so different. The negative charge far from the source affects the reverse read since the forward read punches through the region under the trapped charge 86 .

[0050] Applicant believes that the buildup of trapped charge 86 occurs due to slow hot electron programming in the areas away from the drain where the lateral electric field, though smaller, still is enough to inject electrons. Trapped charge 86 is not erased since the erase electric field is only strong enough to erase in the areas very close to the drain.

[0051] Applicant has realized that, to reduce the charge trapping “far” from the bit line junctions, the field far from the junctions must be reduced. However, this field reduction should not adversely affect the programming efficiency. Thus, the high field must be produced near the bit line junction only.

[0052] Reference is now made to FIGS. 4A and 4B which illustrate an NROM cell, constructed and operative in accordance with two preferred embodiments of the present invention. FIGS. 4A and 4B are similar to FIGS. 1 and thus, similar reference numerals refer to similar elements. Reference is also made to FIGS. 5 A and 5 B which are graphs of the lateral channel field and the distribution of channel potential, respectively, for the NROM cells of FIGS. 4A and 4B and for a prior art NROM cell.

[0053] The NROM cell comprises the channel 100 between the bit lines 102 and 104 , the oxide-nitride-oxide sandwich of layers 109 , 110 , 111 , respectively, and the polysilicon gate 112 . A blanket threshold implant is present in the channel, though not shown specifically. In addition, in accordance with preferred embodiments of the present invention, the NROM cell comprises either one or two extra implants self-aligned to each the junction of each bit line with the channel 100 . FIG. 4A shows a Boron implant 120 and FIG. 4B shows Boron implant 120 with a Phosphorous implant 122 .

[0054] The Boron implant 120 is designed to have a maximum concentration near the bit line 102 or 104 while the Phosphorous implant 122 is designed to have a maximum concentration away from the bit line 102 or 104 .

[0055] The single pocket implant of Boron 120 , in the embodiment of FIG. 4 A, increases the threshold voltage level and, correspondingly, the lateral field, of the cell in the area near each bit line. Since Boron creates holes and Phosphorous creates free electrons, the combined profile, in the embodiment of FIG. 4 B, is the difference of the two concentrations throughout the channel. Thus, the “double pocket” implant heightens the lateral field near the bit lines 102 and 104 but significantly reduces the lateral field in the rest of the channel 100 .

[0056] In both embodiments, the implants are used to shape the lateral channel field so that it is high only close to the bit line junction and so that it drops significantly thereafter. This is shown in FIGS. 5A and 5B which graph of the channel field and potential, respectively, versus the location along the channel 100 for the right bit, for both embodiments and for the prior art. For these figures, the left bit line acts as the source and the right bit line acts as the drain. Position 130 is the location of the maximum concentration of Boron and position 132 is the location of the maximum concentration of the Phosphorous implant, if present.

[0057] In each Figure, three curves are shown. For FIG. 5 A, curve 134 indicates the lateral field with only a blanket threshold Vt implant, curve 136 indicates the lateral field with a single pocket implant, and curve 138 indicates the lateral field with the double pocket implant.

[0058] As can be seen in curve 134 , when only a blanket Vt implant is present, the lateral field gently increases in the direction of the drain junction. Similarly for the lateral field of a cell with a single pocket implant, except that, as shown in curve 136 , the field is lower throughout most of the channel, increasing significantly in the vicinity of the Boron implant, near the drain junction. In fact, near the drain junction, the cell with the single pocket implant has a stronger lateral field than the cell with no pocket implants (curve 134 ).

[0059] For the double pocket implant, as seen in curve 138 , the lateral field has a sharp dip 139 in the vicinity of the maximum concentration 132 of the Phosphorous implant and increases sharply toward the drain junction. It is noted that the lateral field is higher near the drain for the double implant than for either the single implant or no implant.

[0060] Similarly, for the channel potential of FIG. 5B . Curve 140 graphs the potential for an NROM cell without no implants, curve 141 graphs the potential of a cell with the single pocket implant and curve 142 graphs the potential of a cell with the double pocket implant. The channel potential starts at the 0V of the source and drops towards the negative V _d of the drain for all embodiments.

[0061] With the double pocket implant, the drain voltage is present only in the very close vicinity of the drain (curve 142 ). For the single pocket implant (curve 141 ), the drain voltage is spread over a slightly larger area near the drain while for the cell of no implants (curve 140 ), the drain voltage is spread over a significant area away from the drain.

[0062] As indicated by FIGS. 5A and 5B , the single and double pocket implants maintain the effect of the drain voltage (high lateral field and strongly negative voltage level) in the vicinity of the drain. For the double pocket implant, there is a sharp drop-off away from the drain.

[0063] For both embodiments, the generally thin area of effect forces the programmed charge to remain in a thin area of the nitride 110 ( FIGS. 4 ). This improves programming speed when programming ‘this’ bit. Furthermore, since the programmed charge is maintained in an area near the drain, the erase voltage generally removes all of the charge for this bit. The thin area of effect also ensures effective punchthrough when reading the ‘other’ bit.

[0064] Reference is now made to FIG. 6 which illustrates the threshold voltage level throughout the cell after implantation. As can be seen, the threshold voltage level is low (labeled 150 ) throughout most of the channel with peaks 152 near the bit line junctions 102 and 104 . The height and width of the peaks 152 is a function of the number of implants (one or two) and the locations of maximum concentration of the implant or implants. In general, the general threshold voltage level 150 is at a low level, of about 1V, while the peaks 152 reach a much higher level, such as about 2V.

[0065] Thus, in the areas to be programmed, the threshold voltage level of the cell starts higher than the standard 1.5V. Furthermore, once a bit has been programmed, for example, with a single unit −Q of charge, the threshold voltage level in the area of interest rises to a programmed level 154 , such as of 3V. The programmed threshold voltage level is indicated with dashed lines.

[0066] Upon erasure, the threshold voltage level of the cell, as indicated with dotted lines, drops to the general level 150 of the center of the cell. As this is below the original threshold voltage level 152 in the drain area, the cell is now erased to a positive charge level, for example of +Q, at least in the area near the bit line junction. To reprogram the cell, one must provide enough negative charge to counter the positive erase state and to bring the cell to the negative level of being programmed. This is opposed to the prior art which programs to the negative level of being programmed (e.g. −2Q) and erases to the initial, non-charged state (e.g. 0).

[0067] It will be appreciated that measuring the change in state between the negative charge, such as −Q, of programming and the positive charge, such as +Q, of erasure is generally easier than measuring, as in the prior art, the difference between the negative charge −2Q of programming and the non-charged state of erasure 0Q. It will further be appreciated that the ratio of positive to negative charge does not have to be equal; other ratios, such as 0.25:1.75 are also possible and are incorporated into the present invention.

[0068] It will still further be appreciated that the low amounts of charge (−1Q or −1.75Q vs. −2Q) reduce the size of the field caused by the presence of charge within the nitride layer. This reduced field helps retain the charge within its desired location.

[0069] Furthermore, since only the threshold voltage level of the peaks 152 is actively involved in the programming and erasure process, the general level 150 of the center of the cell can be set to any desired low level.

[0070] Reference is now made to FIGS. 7A, 7B , 7 C, 7 D, 7 E and 7 F which illustrate an exemplary method of producing the cell of the present invention.

[0071] Initially, and as shown in FIG. 7 A, the oxide, nitride and oxide layers 160 , 162 and 164 , respectively, are grown on top of a substrate 166 , to form the basis of the ONO structure. Typical thicknesses of layers 160 , 162 and 164 are 50-100 Å, 20-50 Å, 50-100 Å, respectively. If desired, a p-well or blanket threshold implant, of 5-10 ³ per cm ³ can be provided to the substrate 166 prior to growing the ONO layers.

[0072] A bit line mask 168 is laid down next. The mask is formed of columns laid over the locations of the future channels. The bit lines are to be implanted between the columns 168 and are thus, self-aligned to the future channels. The bit line mask can be formed of a hardened photoresist or of a thick oxide.

[0073] In accordance with a preferred embodiment of the present invention, the bit line mask 168 is a layer of photoresist hardened with ultraviolet (UV) after being laid down. This makes a hard mask which is not removable using the standard photoresist removal solvents.

[0074] An alternative bit line mask 168 can be formed of a thick oxide layer, of a minimal thickness of 1000 Å. Such a mask is formed by first depositing a thick oxide layer, typically utilizing the low pressure, chemical vapor deposit (LPCVD) process. A layer of photoresist is then deposited in the desired column pattern after which the oxide found between the photoresist columns is etched away, typically using a dry etch process. The photoresist layer is removed and the thick oxide, bit line mask 168 remains. The thick oxide mask cannot be removed during standard, solvent, photoresist removal techniques.

[0075] As shown in FIG. 7 B, the ONO layers are etched, using a dry etch or wet / dry combination, to remove the oxide and nitride layers between the columns of the bit line mask 168 . The lower oxide layer 160 remains between the columns of the bit line mask 168 to implant through the oxide. This is commonly performed in the art to reduce channeling.

[0076] The bit lines 104 are then implanted between the columns of the bit line mask 168 . Typically, the implant operation is 45 Kev of Arsenic, up to a dose of 2-6×10 ¹⁵ per cm ² . Other implants and dosage levels are also contemplated and are within the scope of the present invention.

[0077] At this point, the right and left bit line junctions of each cell are separately implanted. For each side, the same operation occurs. A threshold pocket implant, of one or two implant materials, is provided at an angle to the vertical, thereby implanting, in a self-aligned manner, into the bit line junctions as well as into part of the open bit lines near the bit line junctions. The process is then repeated for the other side.

[0078] FIG. 7C shows the operation for left bit line junctions 170 of one row of cells and indicates the threshold implant with arrows 172 . The implant can be any suitable threshold pocket implant. For a single implant, it can be Boron at 30-120 Kev up to a dose of 1-5×10 ¹³ per cm ² . The second implant, if there is one, can be Phosphorous at 30-100 Kev up to a dose of 0.5-2.5×10 ¹³ per cm ² . The remaining discussion of the manufacturing process will use the term “implant” to refer to either a single implant or a double implant unless otherwise stated.

[0079] The implant is at an angle of 15-45° to the right of vertical. Since the bit line mask 168 covers the channels of all cells, the implant has access only to the left bit line junctions. The implant is to the right of the vertical since the left bit line junctions are on the right of the open bit lines (which is to the left of the neighboring channel). As indicated by the arrows 172 , the angled implant accesses the left bit line junction and a portion of the open bit lines to the left of the junction. The implant is, thus, self-aligned to the left bit line junctions 170 of the channels.

[0080] The implant dosage must be high enough to ensure sufficient implantation into the channel portion of the bit line junction such that some implant remains even if the bit line later diffuses into the channel. The implant which reaches the rightmost portion of the bit line has no effect on the function of the cell; instead, the implant adds to the bit line implant dosage. Since the threshold implant dosage is two orders of magnitude lower than the bit line implant dosage, it does not affect the dosage within the bit line.

[0081] The choice of angle is typically based on the desired location of maximum concentration for each implant material and is typically 15-45°. The thickness of the bit line mask 168 affects the amount of shadowing and is a function of the angle of the implant, as follows:

[0082] Let S be the amount of the bit line 104 , from the bit line mask 168 , to be shadowed, let h 1 be the thickness of the bit line mask 168 and let a be the angle from the vertical of the implant, then:

S=h 1 *tanα

[0083] For example, if the desired shadowing S is 800 Å and the angle α is 20°, then the thickness h 1 is 2197 Å.

[0084] FIG. 7D illustrates the threshold implant operation for the right bit line junctions 176 . The implant, labeled by arrows 174 , is at the same angle as before; however, for the right bit line junctions 176 , the implant angle is to the left of vertical.

[0085] It will be appreciated that the bit line mask 168 is both a bit line mask and a threshold pocket implant mask. Thus, the bit line implant can occur before the pocket implants, as shown, or afterwards. It will further be appreciated that the order for implanting the pocket implant into the right and left bit line junctions is not significant nor does it affect the self-alignment of the implants to the bit line junctions.

[0086] Once all of the relevant bit line junctions have been implanted, the bit line mask 168 is removed. For UV hardened photoresist, this process involves a plasma removal process of the top photoresist layer followed by standard solvent photoresist removal techniques. If the bit line mask 168 is formed of a thick oxide layer, it is removed with a standard wet etch.

[0087] Following removal of all of the photoresist elements, the sacrificial oxide layer 160 is removed using a wet etch. The result is shown in FIG. 7E . Within substrate 166 are the bit lines 104 and the implanted bit line junctions 170 and 176 . If the bit line mask 168 is formed of a thick oxide layer, the sacrificial oxide layer 160 is removed together with the bit line mask.

[0088] The memory array is now finished in accordance with standard CMOS (complementary, metal-oxide semiconductor) process techniques. The two steps of interest are the gate oxide growth step and the polysilicon word line deposition.

[0089] A gate oxide layer is now thermally grown over the entire array using standard oxidation techniques. The gate oxide layer 20 is typically grown to a thickness of 30-150 Å over the channels 100 .

[0090] In the array, the oxidation step causes oxide, labeled 178 in FIG. 7 F, to grow over the bit lines 104 . Due to the presence of the nitride in the ONO elements, little oxide is added onto the top of the ONO elements. Due to the presence of implant in the bit line, the oxide over the bit line is thick. If the bit line oxide must be even thicker, an oxidation step can also occur after the implant steps.

[0091] As noted hereinabove and as shown in FIG. 7 F, when the gate oxide is grown, the gate oxide layer 20 is 2-3 times thicker over the bit lines 104 due to the presence therein of the bit line implant material. If the gate oxide is deposited, this is not true.

[0092] It is noted that the oxidation step occurs after the bit lines have been implanted. If the oxide is grown, the bit lines might diffuse outwardly for lack of an oxide cap. This can contaminate the CMOS area of the chip. In accordance with a preferred embodiment of the present invention, the oxide growth step provides a small amount of oxygen to the oven while slowly ramping the temperature therein, thereby capping the chip with a thin layer of oxide. The ramp typically begins at 700° C. Once the desired temperature is reached, the full amount of oxide should be placed in the oven.

[0093] The final step is the deposition of the polysilicon gates and word lines 22 , in accordance with standard deposition techniques. The result is the row shown in FIG. 7E .

[0094] The standard CMOS backend continues at this point without any special mask to protect the array.

[0095] Reference is now briefly made to FIGS. 8A and 8B which show alternative embodiments of the present invention for single bit NROM cells. FIG. 8A shows an NROM cell having a single pocket implant 120 on the right side of the cell while FIG. 8A shows an NROM cell having two pocket implants 120 and 122 on the right side of the cell.

[0096] It will be appreciated that the two, single bit cells of FIGS. 8A and 8B have the same properties as the double bit cells of FIGS. 4A and 4B . Thus, the improved qualities of the lateral field and channel potential of FIGS. 5A and 5B , respectively, are applicable to the cells of FIGS. 8A and 8B during programming, when the right bit line 104 is the drain.

[0097] It will further be appreciated that the selective threshold levels of FIG. 6 are also applicable to the single bit cells of FIGS. 8A and 8B . Specifically, the threshold voltage level is low (labeled 150 ) throughout most of the channel with peaks 152 near the right bit line junction 104 .

[0098] It will be appreciated by persons skilled in the art that the present invention is not limited by what has been particularly shown and described herein above. Rather the scope of the invention is defined by the claims that follow: